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The chapter is based on the papers presented at International Test Synthesis Workshop (ITSW’03) [168], 2003, Design and Diagnostics of Electronic Circuits & Systems (DDECS’03), 2003 [169], and VLSI Test Symposium (VTS’04), 2004 [174].
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© 2005 Springer
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(2005). Defect-Aware Test Scheduling. In: Introduction to Advanced System-on-Chip Test Design and Optimization. Frontiers in Electronic Testing, vol 29. Springer, Boston, MA. https://doi.org/10.1007/0-387-25624-5_14
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DOI: https://doi.org/10.1007/0-387-25624-5_14
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4020-3207-3
Online ISBN: 978-0-387-25624-5
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