Hierarchical Symbolic Analysis and Hierarchical Model Order Reduction

6. Summary

In this chapter, we have presented a general hierarchical linear network simulation and modeling technique in s-domain. This hierarchical reduction method can be viewed as generalized Y - Δ transformation discussed in the previous chapters. The simulation and modeling are done by subcircuit suppression in a hierarchical way and by rational function approximation, which generates exact or order-reduced cancellation-free admittances in the reduced network matrices. The presented method works on circuit matrices formulated by MNA formulation and can be applied to any linear circuit.

On the theoretical side, we studied how common factors are generated in the general subcircuit reduction process and presented some theoretical results. On the practical side, we presented a novel de-cancellation strategy based on determinant decision diagrams to derive the cancellation-free rational functions for determinants generated from subcircuit reduction. The resulting method can be used for modeling of both linear(ized) analog circuits, which typically are active circuits with controlled sources, and passive interconnect circuits. Experimental results have validated the proposed method on some linear analog circuits and large RLC interconnect circuits.