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References
J. Craninckx and M. Steyaert, “A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-µm CMOS,” IEEE J. Solid-State Circuits, vol. 31, pp. 890–897, July 1996
A. Benachour, S. Embabi, and A. Ali, “A 1.5GHz sub-2mW CMOS dual modulus prescaler,” in Proc. IEEE Custom. Integrated Circuits Conf. (CICC), San Diego, CA, May 1999, pp. 613–616
N. Krishnapura and P. Kinget, “A 5.3-GHz programmable divider for HiperLAN in 0.25-µm CMOS,” IEEE J. Solid-State Circuits, vol. 35, pp. 1019–1024, July 2000
H. Knapp, J. Bock, M. Wurzer, G. Ritzberger, K. Aufinger, and L. Treitinger, “A 2-GHz/2-mW and 12-GHz/30-mW dual-modulus prescalers in silicon bipolar technology,” IEEE J. Solid-State Circuits, vol. 36, pp. 1420–1423, Sept. 2001
C. Vaucher, I. Ferencic, M. Locher, S. Sedvallson, U. Voegeli, and Z. Wang, “A family of low-power truly modular programmable dividers in standard 0.35-µm CMOS technology,” IEEE J. Solid-State Circuits, vol. 35, pp. 1039–1045, July 2000
J. Navarro Soares, Jr. and W. Van Noije, “A 1.6-GHz dual modulus prescaler using extended true-single-phasc-clock CMOS circuit technique (E-TSPC),” IEEE J. Solid-State Circuits, vol. 34, pp. 97–102, Jan. 1999
H. Rategh, H. Samavati, and T. Lee, “A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver,” IEEE J. Solid-State Circuits, vol. 35, pp. 780–787, May 2000
D. Theil, C. Durdodt, A. Hanke, S. Heine, S. Waasen, D. Seippel, D. Pham-Stabner, and K. Schumacher, “A fully integrated CMOS frequency synthesizer for Bluetooth,” in Proc. IEEE Radio Frequency Integrated Circuits (RFIC) Symp., Phoenix, AZ, May 2001, pp. 103–106
J. Craninckx and M. Steyaert, “A fully integrated CMOS DCS-1800 frequency synthesizer,” IEEE J. Solid-State Circuits, vol. 33, pp. 2054–2065, Dec. 1998
C. Lam and B. Razavi, “A 2.6-GHz/5.2-GHz frequency synthesizer in 0.4-µm CMOS technology,” IEEE J. Solid-State Circuits, vol. 35, pp. 788–794, May 2000
S. Willingham, M. Perrott, B. Setterberg, A. Grzegorek, and B. MaFarland, “An integrated 2.5GHz ΣΔ frequency synthesizer with 5&Gms settling time and 2Mb/s closed-loop modulation,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2000, pp. 200–201
T. Lee and B. Razavi, “A stabilization technique for phase-locked frequency synthesizer,” in Proc. 2001 Symp. VLSI Circuits, Kyoto, Japan, June 2001, pp. 39–42
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(2005). Prototype Measurement Results. In: CMOS PLL Synthesizers: Analysis and Design. The International Series in Engineering and Computer Science, vol 783. Springer, Boston, MA. https://doi.org/10.1007/0-387-23669-4_8
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DOI: https://doi.org/10.1007/0-387-23669-4_8
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