Summary
Throughout this chapter a number of approaches to handle test power have been outlined. Three orthogonal directions have been identified based on: test set dependence, the number of clock cycles required to apply a test vector and the location of test sources and sinks. Since test resource sharing determines resource allocation conflicts power-constrained test scheduling was also summarized.
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© 2004 Springer Science + Business Media, Inc.
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(2004). Approaches to Handle Test Power. In: Power-constrained Testing of VLSI Circuits. Frontiers in Electronic Testing, vol 22B. Springer, Boston, MA. https://doi.org/10.1007/0-306-48731-4_3
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DOI: https://doi.org/10.1007/0-306-48731-4_3
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4020-7235-2
Online ISBN: 978-0-306-48731-6
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