A Design Space Exploration Methodology

Conclusions

This chapter addressed the problem of design space exploration of embedded system architectures considering performance and power consumption as the most relevant constraints. In particular, an exploration methodology to reduce simulation time while preserving acceptable design accuracy has been proposed and experimentally assessed by considering the design of the memory subsystem of two real-world embedded systems. Experimental results have shown a speed-up in simulation time of almost two orders of magnitude and an average distance from the optimal configuration below 16%. Furthermore, this methodology allows the designer to save analysis time since the number of configurations to be compared is significantly reduced.

Beyond the evaluation of the impact of the variation of cache-related parameters from the power-performance joint perspective, the next step of our work will aim at estimating the effects of power-aware compiler optimizations on the Energy*Delay metric at the system-level also for superscalar architectures.