A Micro-Architectural Optimization for Low Power

Conclusions

In this chapter, optimization in view of power consumption has been discussed with reference to the data path of a VLIW microprocessor and to the instructions that access the Register File. The next chapter is devoted to the second power optimization methodology that consists of an efficient exploration of the architectural parameters of the memory sub-systems, from the energy-delay joint perspective. The aim is to find the best configuration of the memory hierarchy without performing an exhaustive analysis of the parameters space. The target system architecture includes the processor, separated instruction and data caches, the main memory, and the system buses.