Skip to main content

Guaranteeing the Quality of Services in Networks on Chip

  • Chapter
Networks on Chip

Abstract

Users expect a predictable quality of service (QoS) of embedded systems, even for future, more dynamic, applications. System-on-chip designers use networks on chip (NOC) to solve deep submicron problems, and to divide global problems into local, decoupled problems. NOCs provide services through protocol stacks, and introducing guaranteed services enables IP re-use and platform-based design. It also provides globally predictable behaviour, as required by the user, when combining local, decoupled solutions. There are several levels of QoS commitment (correctness, completion, completion bounds), with increasing cost. A combination of guaranteed and best-effort (no commitment) services combines their respective attractive features: predictable behaviour, and good average resource utilisation. The Aethereal NOC is an example of this approach, and forms the basis of a QoS-based design style, as advocated in this chapter.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 129.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Semiconductor Industry Association. The International Technology Roadmap for Semiconductors. 2001.

    Google Scholar 

  2. Paul Wielage and Kees Goossens. Networks on silicon: Blessing or nightmare? In Euromicro Symposium On Digital System Design, Dortmund, Germany, September 2002. Keynote speech.

    Google Scholar 

  3. T. N. Theis. The future of interconnection technology. IBM journal of research development, 44(3):379–390, May 2000.

    MathSciNet  Google Scholar 

  4. Marcel J. Pelgrom, Hans P. Tuinhout, and Maarten Vertregt. Transistor matching in analog CMOS applications. In IEDM, pages 915–918, 1998.

    Google Scholar 

  5. K. Keutzer, S. Malik, A. Richard Newton, Jan M. Rabaey, and A. Sangiovanni-Vincentelli. System-level design: Orthogonalization of concerns and platform-based design. IEEE Trans. on CAD of Integrated Circuits and Systems, 19(12):1523–1543, 2000.

    Article  Google Scholar 

  6. Jens Muttersbach, Thomas Villiger, and Wolfgang Fichtner. Practical design of globally-asynchronous locally-synchronous systems. In 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC), April 2000.

    Google Scholar 

  7. Paul Stravers and Jan Hoogerbrugge. Homogeneous multiprocessing and the future of silicon design paradigms. In VLSI-TSA, 2001.

    Google Scholar 

  8. Ken Mai, Tim Paaske, Nuwan Jayasena, Ron Ho, William J. Dally, and Mark Horowitz. Smart memories: A modular reconfigurable architecture. In ISCA, June 2000.

    Google Scholar 

  9. William J. Dally and Brian Towles. Route packets, not wires: On-chip interconnection networks. In Design Automation Conference, pages 684–689, June 2001.

    Google Scholar 

  10. Théodore Marescaux, Andrei Bartic, Dideriek Verkest, Serge Vernalde, and Rudy Lauwereins. Interconnection networks enable fine-grain dynamic multitasking on FPGAs. FPL, 2002. LNCS 2438.

    Google Scholar 

  11. Edson L. Horta, John W. Lockwood, David E. Taylor, and David Parlour. Dynamic hardware plugins in an FPGA with partial run-time configuration. In Design Automation Conference, June 2002.

    Google Scholar 

  12. Lance Hammond, Basam A. Hayfeh, and Kunle Olokotun. A single-chip multiprocessor. IEEE Computer, pages 79–85, September 1997.

    Google Scholar 

  13. Jaehyuk Huh, Stephen W. Keckler, and Doug Burger. Exploring the design space of future CMPs. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT), 2001.

    Google Scholar 

  14. Eylon Caspi, André DeHon, and John Wawrzynek. A streaming multithreaded model. In Third Workshop on Media and Stream Processors (MSP-3), December 2001.

    Google Scholar 

  15. M. Sgroi, M. Sheets, A. Mihal, K. Keutzer, S. Malik, J. Rabaey, and A. Sangiovanni-Vincentelli. Addressing the system-on-a-chip interconnect woes through communication-based design. In Design Automation Conference, pages 667–672, June 2001.

    Google Scholar 

  16. Luca Benini and Giovanni De Micheli. Networks on chips: A new SoC paradigm. IEEE Computer, 35(1):70–80, 2002.

    Google Scholar 

  17. K. Goossens, J. van Meerbergen, A. Peeters, and P. Wielage. Networks on silicon: Combining best-effort and guaranteed services. In Proceedings of Design Automation and Test Conference in Europe, pages 423–425, March 2002.

    Google Scholar 

  18. A. Ferrari and A. Sangiovanni-Vincentelli. System design: traditional concepts and new paradigms. In International Conference on Computer Design, pages 2–12, 1999.

    Google Scholar 

  19. J. D. Day and H. Zimmerman. The OSI reference model. In Proceedings of the IEEE, volume 71, pages 1334–1340, 1983.

    Article  Google Scholar 

  20. K. G. W. Goossens and O. P. Gangwal. The cost of communication protocols and coordination languages in embedded systems. In Farhad Arbab and Carolyn Talcott, editors, Coordination languages and models, number 2315 in Lecture notes in computer science, pages 174–190. Springer Verlag, April 2002.

    Google Scholar 

  21. Steve Deering. Watching the waist of the protocol hourglass. In 6th IEEE International Conference on Network Protocols, October 1998. Keynote speech.

    Google Scholar 

  22. VSI Alliance. Virtual component interface standard, 2000.

    Google Scholar 

  23. OCP International Partnership. Open core protocol specification, 2001.

    Google Scholar 

  24. Andrei Radulescu and Kees Goossens. Communication services for networks on silicon. In Shuvra Bhattacharyya, Ed Deprettere, and Juergen Teich, editors, Domain-Specific Processors: Systems, Architectures, Modeling, and Simulation. Marcel Dekker, December 2002.

    Google Scholar 

  25. Vijay P. Kumar, T. V. Lashman, and Dimitrios Stiliadis. Beyond best effort: Router architectures for the differentiated services of tomorrow’s internet. IEEE Communications Magazine, pages 152–164, May 1998.

    Google Scholar 

  26. Girish Varatkar. Traffic analysis for on-chip networks design of multimedia applications. In Design Automation Conference, June 2002.

    Google Scholar 

  27. Sungjoo Yoo, Kyoungseok Rha, Youngchul Cho, Jinyong Kung, and Kiyoung Choi. Performance estimation of multiple-cache IP-based systems: Case study of an interdependency problem and application of an extended shared memory model. In International Workshop on Hardware/Software Codesign, May 2002.

    Google Scholar 

  28. Pierre Guerrier and Alain Greiner. A generic architecture for on-chip packet-switched interconnections. In Proceedings of Design Automation and Test Conference in Europe, pages 250–256, 2000.

    Google Scholar 

  29. Pierre Guerrier. Un Réseau D’Interconnexion pour Systémes Intégrés. PhD thesis, Université Paris VI, March 2000.

    Google Scholar 

  30. Davide Bertozzi, Luca Benini, and Giovanni De Micheli. Low power error resilient encoding for on-chip data buses. In Proceedings of Design Automation and Test Conference in Europe, March 2002.

    Google Scholar 

  31. E. Rijpkema, K. Goossens, A. Radulescu J. van Meerbergen, P. Wielage, and E. Waterlander. Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip. In Proceedings of Design Automation and Test Conference in Europe, March 2003.

    Google Scholar 

  32. Edwin Rijpkema, Kees Goossens, and Paul Wielage. A router architecture for networks on silicon. In Proceedings of Progress 2001, 2nd Workshop on Embedded Systems, Veldhoven, the Netherlands, October 2001.

    Google Scholar 

  33. André DeHon. Robust, high-speed network design for large-scale multiprocessing. A.I. Technical report 1445, Massachusetts Institute of Technology, Artificial Intelligence Laboratory, September 1993.

    Google Scholar 

  34. Hui Zhang. Service disciplines for guaranteed performance service in packet-switching networks. Proceedings of the IEEE, 83(10): 1374–96, October 1995.

    Google Scholar 

  35. Jennifer Rexford, John Hall, and Kang G. Shin. A router architecture for real-time communication in multicomputer networks. IEEE Transactions on Computers, 47(10):1088–1101, October 1998.

    Article  Google Scholar 

  36. ATM Forum. ATM User-Network Interface Specification. Prentice Hall, July 1994. Version 3.1.

    Google Scholar 

  37. Drew Wingard. MicroNetworks-based integration for SOCs. In Design Automation Conference, 2001.

    Google Scholar 

  38. Kanishka Lahari, Anand Raghunathan, and Ganesh Laskhminarayana. Lotterybus: A new high-performance communication architecture for system-on-chip designs. In Design Automation Conference, June 2001.

    Google Scholar 

  39. Jeroen A.J. Leijten, Jef L. van Meerbergen, Adwin H. Timmer, and Jochen A.G. Jess. Stream communication between real-time tasks in a high-performance multiprocessor. In Proceedings of Design Automation and Test Conference in Europe, pages 125–131, 1998.

    Google Scholar 

  40. Paul J.M. Havinga. Mobile Multimedia Systems. PhD thesis, University of Twente, The Netherlands, February 2000.

    Google Scholar 

  41. Kyeong Keol Ryu, Eung Shin, and Vincent J Mooney. A comparison of five different multiprocessor SoC bus architectures. In Euromicro, 2001.

    Google Scholar 

  42. Tycho van Meeuwen, Arnout Vandecappelle, Allert van Zelst, Francky Catthoor, and Diederik Verkest. System-level interconnect architectures exploration for custum memory organizations. In International Symposium on System Synthesis, pages 13–18, October 2001.

    Google Scholar 

  43. Milenko Drinic, Darko Kirovski, Seapahn Meguerdichian, and Miodrag Potknojak. Latency-guided on-chip bus network design. In Proc. of IEEE/ACM International Conference on Computer Aided Design, pages 420–423, November 2000.

    Google Scholar 

  44. John Bainbridge and Steve Furber. CHAIN: A delay-insensitive chip area interconnect. IEEE Micro, 22(5), 2002.

    Google Scholar 

  45. Frederic Chong, Henry Minsky, André deHon, Matthew Becker, Samuel Peretz, Eran Egozy, and Frank F. Knight, Jr. Metro: A router architecture for high-performance, short-haul routing networks. In International Symposium on Computer Architecture, April 1994.

    Google Scholar 

  46. Faraydon Karim, Anh Nguyen, Sujit Dey, and Ramesh Rao. On-chip communication architecture for OC-768 network processors. In Design Automation Conference, June 2001.

    Google Scholar 

  47. André DeHon. Rent’ rule based switching requirements. In SLIP, April 2001. Extended abstract.

    Google Scholar 

  48. Shashi Kumar, Axel Jantsch, Juha-Pekka Soininen, Martti Forsell, Mikael Millberg, Johny Öberg, Tiensyrjä, and Ahmed Hemani. A network on chip architecture and design methodology. In ISVLSI, 2002.

    Google Scholar 

  49. David Whelihan and Herman Schmit. Memory optimization in single chip network switch fabrics. In Design Automation Conference, June 2002.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2003 Kluwer Academic Publishers

About this chapter

Cite this chapter

Goossens, K. et al. (2003). Guaranteeing the Quality of Services in Networks on Chip. In: Jantsch, A., Tenhunen, H. (eds) Networks on Chip. Springer, Boston, MA. https://doi.org/10.1007/0-306-48727-6_4

Download citation

  • DOI: https://doi.org/10.1007/0-306-48727-6_4

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4020-7392-2

  • Online ISBN: 978-0-306-48727-9

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics