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References
A. Deutsch, H. Smith, G.A. Katopis, W.D. Becker, P.W. Coteus, C.W. Surovic, G.V. Kopcsay, B.J. Rubin, R.P. Dunne, T. Gallo, D.R. Knebel, B.L. Krauter, L.M. Terman, G.A. Sai-Halasz, and P.J. Reslte. “The importance of inductance and inductive coupling for on-chip wiring”. In Topical Meeting on Electrical performance of Electronic Packages, 1997.
T. Mido and K. Asada. “Crosstalk noise in high density and high speed interconnections due to inductive coupling”. In Asia-South Pacific Design Automation Conference, 1997.
Roth J.P., Bouricius W.G., and Schneider P.R. “Programmed algorithms to compute tests to detect and distinguish between failures in logic circuits”. IEEE Trans. on Electronic Computers, EC-16(10), October 1967.
Goel P. “An implicit enumeration algorithm to generate tests for combinational logic circuits”. IEEE Trans. on Computers, C-30(3), March 1981.
Fujiwara H. and Shimono T. “On the acceleration of test generation algorithms”. IEEE Trans. on Computers, C-32(12), December 1983.
Krstic A., Jiang Y. M., and Cheng K.T. “Pattern Generation for Delay Testing and Dynamic Timing Analysis Considering Power-Supply Noise Effects”. IEEE Transactions On Computer Aided Design of Integrated Circuits and Systems, 16(3), March 2001.
Moll F. and Rubio A. “Methodology of Detection of Spurious Signals in VLSI Circuits”. In Proc. of European Test Conference, 1993.
Moll F., Roca M., Marche D., and Rubio A. “Detectability of Spurious Signals with Limited Propagation in Combinational Circuits”. In IEEE 3rd Asian Test Symposium, November 1994.
Goldstein L. “Controlability/observability analysis of digital circuits”. IEEE Trans. on Circuits and Systems, 1979.
Brglez F. and Fujiwara H. “A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran”. In International Symposium on Circuits and Systems, June 1985.
Chen Wei-Yu, Gupta Sandeep K., and Breuer Melvin A. “Test Generation for Crosstalk-Induced Faults: Framework and Computational Results”. Journal of Electronic Testing: Theory and Applications, 18(1), February 2002.
Chen Wei-Yu, Gupta Sandeep K., and Breuer Melvin A. “Test Generation in VLSI Circuits for Crosstalk Noise”. In Proc. International Test Conference, 1998.
Rodriguez R., Pineda J., and Volf P. “Resistance characterization for weak open defects”. IEEE Design and Test of Computers, September 2002.
Roca M. and Rubio A. “Current Testability Analysis of Feedback Bridging Faults in CMOS circuits”. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 14(10), October 1995.
Suehle J. W. “Ultrathin gate oxide reliability: Physical models, statistics, and characterization”. IEEE Transactions On Electron Devices, 49(6), June 2002.
Segura J. and Rubio A. “A detailed analysis of CMOS SRAM’s with gate oxide short defects”. IEEE Journal of Solid State Circuits, 32(10), October 1997.
Beasley J., Righter A.W., Apodaca C.J., Pour-Mozafari S., and Huggett D. “Idd pulse response testing applied to complex CMOS ICs”. In Proc. International Test Conference, 1997.
Makki R., Shyang-Tai S., and Nagle T. “Transient power supply current testing of digital CMOS circuits”. In Proc. International Test Conference, 1995.
Sachdev M., Janssen P., and Zieren V. “Defect detection with transient current testing and its potential for deep sub-micron CMOS ICs”. In Proc. International Test Conference, 1998.
Segura J., De Paul I., Roca M., Isern E., and Hawkins C. “Experimental analysis of transient current testing based on charge observation”. IEE Electronic Letters, 35(6), March 1999.
Picos R., Roca M., Isern E., and Garcia Moreno E. “Experimental results on BIC sensors for transient current testing”. Journal of Electronic Testing: Theory and Applications, 16(3), 2000.
Singh A., Plusquellic J., and Gattiker A. “Power supply transient signal analysis under real process and hardware models”. In IEEE VLSI Test Symposium, 2002.
Jiang W. and Vinnakota B. “Statistical threshold formulation for dynamic Idd test”. IEEE Transactions On Computer Aided Design of Integrated Circuits and Systems, 21(6), June 2002.
Sun X., Kim S., and Vinnakota B. “Crosstalk Fault Detection by Dynamic Idd”. In Proc. of the International Conference on Computer Aided Design ICCAD, 2001.
Jiang W. and Vinnakota B. “IC Test with the Energy Consumption Ratio”. In Proc. of the Design Automation Conference, 1999.
Bay X., Dey S., and Rajski J. “Self-Test Methodology for At-Speed Test of Crosstalk in Chip Interconnects”. In Proc. of the Design Automation Conference, 2000.
M. Cuviello, S. Dey, Xiaoliang Bai, and Yi Zhao. “Fault modeling and simulation for crosstalk in system-on-chip interconnects”. In International Conf. on Computer Aided Design (ICCAD), 1999.
Metra C., Di Francescantoni S., Favalli M., and Ricco B. “Scan flip-flops with on-line testing ability with respec to input delay and crosstalk faults”. Microelectronics Journal, 34, 2003.
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(2004). Noise Detection and Testing in Logic Circuits. In: Interconnection Noise in VLSI Circuits. Springer, Boston, MA. https://doi.org/10.1007/0-306-48719-5_6
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DOI: https://doi.org/10.1007/0-306-48719-5_6
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