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Pin-Level Hardware Fault Injection Techniques

  • Pedro Gil
  • Sara Blanc
  • Juan José Serrano
Part of the Frontiers in Electronic Testing book series (FRET, volume 23)

Abstract

Among hardware fault injection techniques involved in the validation of fault tolerant systems, pin-level fault injection is one of the more relevant techniques of the last years. The technique is suitable for injecting faults in the real system under test or in a prototype. Tools based on this technique are generic being possible the reusability of the tool. They are developed externally to the target causing no execution overhead on the system. This chapter presents a general overview about pin-level fault injection with a state of the art including the more remarkable features of the technique. Finally the tool AFIT developed by the Polytechnic University of Valencia (Spain), is described as a real implementation of the technique. Moreover, it presents an example about the methodology carried out in fault injection campaigns and the usability of the pin-level fault injection technique.

Key words

Dependability pin-level fault injection fault tolerance hardware fault injection techniques 

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Copyright information

© Kluwer Academic Publishers 2003

Authors and Affiliations

  • Pedro Gil
    • 1
  • Sara Blanc
    • 1
  • Juan José Serrano
    • 1
  1. 1.Polytechnic University of Valencia, Fault Tolerant Systems Group (GSTF)Spain

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