High-Level Simulation of Substrate Noise Generation in Complex Digitlal Systems

Abstract

With increasing clock frequencies and resolution requirements in mixed-mode telecom circuits, substrate noise is becoming more and more a major obstacle for single chip integration. To simulate the performance degradation of the sensitive analog circuits the total amount of the generated substrate noise must be known. Existing approaches usually extract the model of the substrate from layout information and then simulate the extracted transistor-level netlist with this substrate model using a transistor-level simulator. For large digital circuits, the substrate simulation is however not feasible with a transistor-level simulator. We have developed a high-level methodology to simulate this substrate noise generation in EPI substrates by taking the noise coupling from the switching gates and also from the supply rails into account. Experimental results show an error of 5% in the RMS value of the substrate noise generation with respect to a full SPICE simulation for a 1K gate circuit, while maintaining a speedup of 3 orders of magnitude with respect to SPICE simulations. The approach has also been applied to the 86K digital ASIC introduced in chapter 2 and compared to measurements.