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SOI Materials

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SOI Design
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References

  1. C. Y. Chang and S. M. Sze, Editors, “ULSI Devices”, John Wiley & Sons, Inc., ISBN 0-471-24067-2

    Google Scholar 

  2. A. Wagpmans, et. al., “3.5mW 2.5GHz Diversity Receiver and a 1.2mW 3.6GHz VCO in Silicon-On-Anything” ISSCC98, paper No. FP 16.3:A

    Google Scholar 

  3. R. Dekker, et. al., “An Ultra Low-Power RF bipolar technology on Glass” IEDM, 1997. pp. 921–923.

    Google Scholar 

  4. M. L. Alles et.al., “Investigating optical metrology issues specific to SIMOX-SOI wafers”, Micro, June 2000

    Google Scholar 

  5. Appendix 1 (2.5)

    Google Scholar 

  6. Appendix 1 (2.6)

    Google Scholar 

  7. R. Hannon, et. al., “0.25 μm Merged Bulk DRAM and SOI Logic using Patterned-SOI”, 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 66–67.

    Google Scholar 

  8. J. Haisma, et. al., Jpn.J.Appl.Phys., vol.25, 1989, pp. 1426.

    Google Scholar 

  9. C. E. Hunt & C. A. Desmond, Proceedings of the First Symposium on Semiconductor Wafer Bonding, 1992, pp. 165.

    Google Scholar 

  10. A. Soderbarg, Proceedings of the First Symposium on Semiconductor Wafer Bonding, 1992, pp.190.

    Google Scholar 

  11. Appendix 1 (2.11)

    Google Scholar 

  12. K. Sakaguchi & T. Yonehara, “SOI Wafers Based on Epitaxial Technology”, Solid State Technology, Jun 2000.

    Google Scholar 

  13. K. Sakaguchi, et. al., Jpn. J.Appl. Phys., vol.34, 1995, pp. 842–847.

    Google Scholar 

  14. P. B. Mumola & G. J. Gardopee, Conference on Solid State Devices and Material, 1995, pp. 256.

    Google Scholar 

  15. “New Technologies for silicon-on-insulator”, European Semiconductor, Feb 2000, pp. 25.

    Google Scholar 

  16. M. I. Current et. al., “Ultrashallow Junctions or Ultrathin SOI”, Solid State Technology, Sept. 2000, pp. 66–77.

    Google Scholar 

  17. H. Lee, et. al., “An Anomalous Device Degradation of SOI Devices with STI”, 2000 IEEE International SOI Conference, Oct. 2000, pp. 132–133.

    Google Scholar 

  18. K. Bernstein & N. J. Rohrer, “SOI Circuit Design Concepts”, Kluwer Academic Publishers, January 2000, ISBN 0-7923-7762-1

    Google Scholar 

  19. T. Houston, et. al. “Novel MESA isolation using CMP for planarization of 0.35/0.25uM SOI”, IEEE International SOI conference, Oct 1995, pp. 110–1.

    Google Scholar 

  20. G. Shahidi, et. al., Proceedings of the 1992 VLSI Symposium, p. 93–94.

    Google Scholar 

  21. G.G. Shahidi, et. al., “A high performance low temperature 0.3 μm CMOS on SIMOX” 1992 Symposium on VLSI Technology, 1992, pp. 106–107.

    Google Scholar 

  22. L. Su, et. al., Proceedings of the 1996 VLSI Symposium.

    Google Scholar 

  23. S. T. Liu, et. al., “Radiation Response of SOI Materials”, Electrochemical Soc. Proc. 1999, pp. 225–230.

    Google Scholar 

  24. G. Shahidi, et. al., ‘Mainstreaming of the SOI Technology,’ Proc. IEEE Inter. SOI Conf, 1999, pp. 1–4.

    Google Scholar 

  25. E. Leobandung, et. al., “High Performance 0.18um SOI CMOS Technology,” IEDM-99, 1999, pp. 679–682.

    Google Scholar 

  26. S. Cristoloveanu, “Architecture of SOI Transistors: What’s Next?”, 2000 IEEE International SOI Conference, Oct. 2000, pp. 1–3.

    Google Scholar 

  27. G. G. Shahidi, et. al., “Device and Circuit Design Issues in SOI Technology”, Proceedings of the IEEE, 1999, pp. 339–346.

    Google Scholar 

  28. G. Shahidi et. al., “A Room Temperature 0.1 μm CMOS on SOI”, IEEE Transactions on Electron Devices, Vol 41, Dec. 1994, pp. 2405–2412.

    Article  Google Scholar 

  29. G. Anthony, et. al., “A 0.2-mm, 1.8-V, SOT, 550-MHz, 64-b PowerPC Microprocessor with Copper Interconnects”, IEEE Journal of Solid State Circuits, Vol. 34, No. 11, Nov. 1999, pp. 1430–4.

    Google Scholar 

  30. Proc. 5th Inter. Workshop on Measurement, Characterization and Modeling of ultrashallow Doping Profiles in Semiconductors, J. Vac. Sci. Technol., 2000, pp. 337–604.

    Google Scholar 

  31. K. Sukegawa, et. al., “High-performance 80-nm Gate Length SOI-cMOS Technology with Copper and Very-low-k Interconnects”, 2000 IEEE Symposium on VLSI Technology Digest of Technical Papers

    Google Scholar 

  32. D. Edelstein, et. al., “Full copper wiring in a sub-0.25 μm CMOS ULSI technology” IEDM Tech.Dig., 1997, pp.773–6.

    Google Scholar 

  33. M. Ikeda, et. al., “Integration of organic low-k material with Cu-damascene employing novel process”, Interconnect Technology Conference, 1998. pp. 131–3.

    Google Scholar 

  34. K. Mistry, et. al., “Scalability Revisited: 100 nm PD-SOI Transistors and Implications for 50 nm Devices”, IEEE VLSI Conference 2000, 0-7803-6308-6, pp. 204–5.

    Google Scholar 

  35. R. Chau, et. al., IEDM Tech. Digest, 1997, pp. 591–594.

    Google Scholar 

  36. E. Leobandung, et. al., “Scalability of SOI technology into 0.13 μm 1.2 V cMOS generation”, IEDM Tech. Digest, 1998, pp. 403–406.

    Google Scholar 

  37. D. Flandre, et. al., “Fully-Depleted-SOI cMOS technology for low-voltage low-power digital/analog/microwave circuits”, Analog Integrated Circuits and Signal Processing. New York: Kluwer, 1998.

    Google Scholar 

  38. J-P. Eggermont, et. al., “Potential and Modeling of 1μm SOI cMOS Operational Transconductance Amplifiers for Applications up to 1 Ghz” IEEE Journal of Solid State Circuits, Vol. 33, No. 4, April 1998, pp 640–643.

    Article  Google Scholar 

  39. S. M. Sze, “Physics of Semiconductor Devices”, John Wiley and Sons, New York.

    Google Scholar 

  40. S. K. H. Fung, et. al., “Impact of the Gate-to-Body Tunneling Current on SOI History Effect”, 2000 IEEE International SOI Conference, Oct. 2000, pp. 122–3.

    Google Scholar 

  41. J. Y. Choi & J. G. Fossum, “Analysis and control of floating body bipolar effect in fully Depleted submicrometer SOI MOSFET’s”, IEEE Trans. Electron Devices, vol.38, 1991, pp. 1384–91.

    Article  Google Scholar 

  42. W. Redman-White, et. al., “Analogue design issues for SOI CMOS” IEEE International SOI Conference, 1996, pp. 6–8.

    Google Scholar 

  43. Y-C. Tseng, et. al., “Local Floating Body Effect in Body-grounded-SOI nMOSFETs”, Proceedings 1997 IEEE International SOI Conference, Oct 1997, pp. 26–7.

    Google Scholar 

  44. O. Rozeau, et. al., “Impact of Floating Body and BS-Tied Architectures on SOI MOSFET’s Radio-Frequency Performances”, 2000 IEEE International SOI Conference, Oct. 2000, pp. 124–5.

    Google Scholar 

  45. Y. C. Tseng, et. al., “Correlation between Low Frequency Noise Overshoot in SOI MOSFETs and Frequency Dependence of Floating Body Effect”, 1997 Symposium on VLSI Technology Digest of Technical Papers, 1997, pp. 99–100.

    Google Scholar 

  46. J. Gautier, et. al., IEDM Tech. Dig., 1995, pp. 61–3.

    Google Scholar 

  47. D. Suh & J. G. Fossum, “Dynamic floating-body instabilities in partially depleted SOI CMOS circuits”, IEDM Technical Digest, 1994, pp. 661–664.

    Google Scholar 

  48. A. Wei, et. al., “Effect of floating-body charge on SOI MOSFET design”, IEEE Trans. Electron Devices, vol. 45, Feb. 1998. pp. 430–438.

    Article  Google Scholar 

  49. F. Assaderaghi, et. al., “History-Dependence of Non-Fully Depleted (NFD) Digital SOI Circuits”, VLSI Tech. Dig., 1996, pp. 122–3.

    Google Scholar 

  50. J. P. Colinge, “Silicon-On-Insulator Technology: Materials to VLSI”, Kluwer Academic Publishers, 1991.

    Google Scholar 

  51. J. Eckhardt et. al., “A SOI specific PLL for 1 GHz microprocessors in 0.25 μ 1.8 V”, ISSCC 1999. pp. 436–437.

    Google Scholar 

  52. A. Nishiiyama, et. al., “Mechanism of the suppression of the floating-body effect for SOI MOSFET’s with SiGe source structure”, Proc. 1996 IEEE Int. SOI Conf., Oct. 1996, pp. 68–69.

    Google Scholar 

  53. K. Suma, et. al., “An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology”, IEEE J. Solid State Circuits, vol. 29, Nov. 1994, pp. 1323–1328.

    Article  Google Scholar 

  54. G. Shahidi et. al., “Partially-Depleted-SOI Technology for Digital Logic”, ISSCC 1999, pp. 426–427.

    Google Scholar 

  55. Silicon-On-Insulator Integrated Circuit Technology, U.S. Patent No. 5,489,792

    Google Scholar 

  56. J.G. Fossum & G.O. Workman, “A comparative analysis of the dynamic behavior of BTG/SOI MOSFETs and circuits with distributed body resistance”, IEEE Transactions on Electron Devices, Oct. 1998, pp. 2138–2145.

    Google Scholar 

  57. K.L. Shepard & D-J. Kim, “Static Noise Analysis for Digital Integrated Circuits in Partially-Depleted Silicon-On-Insulator Technology”, Design Automation Conference, 2000. pp. 239–242.

    Google Scholar 

  58. P-F. Lu, et. al., “Floating-body effects in partially Depleted-SOI CMOS circuits”, IEEE Journal of Solid-State Circuits, August 1997, pp. 1241–1253.

    Google Scholar 

  59. K. L. Shepard, et. al., “Harmony: Static noise analysis for deep-submicron digital integrated circuits”, IEEE Transactions on Computer Aided Design, Aug 1999, pp. 1132–1150.

    Google Scholar 

  60. A. Nève, et. al., “Smart Card Circuits in SOI Technology”, 2000 IEEE International SOI Conference, Oct. 2000, pp. 48–49.

    Google Scholar 

  61. B. M. Tenbroek et. al., Proceedings ESSDERC 1993, Grenoble, France, pp. 189–192

    Google Scholar 

  62. H. Nakayama, et. al., “SOI MOSFET Thermal Conductance and Its Geometry Dependence” 2000 IEEE International SOI Conference, Oct. 2000, pp. 128–9.

    Google Scholar 

  63. B. M. Tenbroek, et. al., “Characterization of layout dependent thermal coupling in SOI CMOS current mirrors”, IEEE Transactions on Electron Devices, Dec. 1996, pp. 2227–2232.

    Google Scholar 

  64. B. M. Tenbroek, et. al., “Measurement and Simulation of Self Heating in SOI CMOS Analogue Circuits”, Proceedings 1997 IEEE International SOI Conference, Oct. 1997, pp. 156–7.

    Google Scholar 

  65. B. M Tenbroek, et. al., “Self-heating effects in SOI MOSFETs and their measurement by small signal conductance techniques”, IEEE Transactions on Electron Devices, Vol. 43, No 12, 1996, pp. 2240–2248.

    Google Scholar 

  66. A. Hastings, “The Art of Analog Layout”, Prentice-Hall, ISBN: 0-13-087061-7, 2000

    Google Scholar 

  67. P. R. Gray & R. G. Meyer, “Analysis and Design of Analog Integrated Circuits, third edition”, Wiley, 1993, ISBN 0-471-57495-3.

    Google Scholar 

  68. M. S. L. Lee, et. al., “Modelling of thin film SOI devices for circuit simulation including per-instance dynamic self-heating effects”, Proc. IEEE Int. SOI Conference, Palm Springs, CA, Oct. 1993, pp. 150–151.

    Google Scholar 

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(2003). SOI Materials. In: SOI Design. Springer, Boston, MA. https://doi.org/10.1007/0-306-48161-8_2

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  • DOI: https://doi.org/10.1007/0-306-48161-8_2

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