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Low Power Design

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SOI Design
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References

  1. H. B. Bakaglu, “Circuits, Interconnections and Packaging for VLSI”, Addision-Wesley, 1990

    Google Scholar 

  2. Rabaey & Pedram, “Low power design methodologies”, Kluwer Academic Publishers, ISBN: 0-7923-9630-8

    Google Scholar 

  3. G. Gerosa, et. al., “A 2.2W 80MHz Superscalar RISC Microprocessor”, IEEE Journal of Solid State Circuits, Vol 29, No. 12, Dec 1994, pp. 1440–1454.

    Article  Google Scholar 

  4. D. Liu & C. Svensson, “Power consumption Estimatino of CMOS VLSI Chips”, IEEE Journal of Solid State Circuits, Vol 29, No. 6, June 1994, pp. 663–670.

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  5. A. P. Chandrakasan, et. al., “Low-power CMOS digital design”, IEEE J. Solid-State Circuits, vol. 27, Apr. 1992, pp. 473–484.

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  6. E. A. Vittoz, “Low-power design: Ways to approach the limits”, ISSCC 1994, pp. 14–18.

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  7. P. Kinget & M. Steyaert, “Analog VLSI integration of massive parallel signal processing systems”, pp. 21–45, Kluwer Academic Publishers, ISBN 0-7923-9823-8, 1997.

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  8. R. Gonzalez, et. al., “Supply and threshold voltage scaling for low power cmos”, IEEE Journal of Solid-State Circuits, 32(8), August 1997, pp. 1210–1216.

    Article  Google Scholar 

  9. J. Ramírez-Angulo, et. al., “A CMOS op-amps for a single supply close to a threshold voltage and with almost rail-to-rail signal swing”, IEEE International Symposium on Circuits and Systems, 1999, pp. 408–411.

    Google Scholar 

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© 2003 Kluwer Academic Publishers

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(2003). Low Power Design. In: SOI Design. Springer, Boston, MA. https://doi.org/10.1007/0-306-48161-8_12

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  • DOI: https://doi.org/10.1007/0-306-48161-8_12

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-0-7923-7640-8

  • Online ISBN: 978-0-306-48161-1

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