Skip to main content

Part of the book series: The International Series in Engineering and Computer Science ((SECS,volume 662))

  • 359 Accesses

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. N. Weste, K. Eshragian, “Principles of CMOS VLSI design”, Reading MA, Addison Wesley, 1985.

    Google Scholar 

  2. J.S. Ward et al., “Figures of merit for VLSI implementations of digital signal processing algorithms”, Proc. Inst. Elec. Eng., vol. 131, part F, pp.64–70, Feb. 1984.

    Google Scholar 

  3. M. Kahumu, M. Kinugawa, “Power-supply voltage impact on circuit performance for half and lower submicrometer CMOS LSI”, IEEE Trans. Electron Devices, vol.37, n0.8, pp.1902–1908, Aug. 1990.

    Google Scholar 

  4. M. Nagata, “Limitations, innovations and challenges of circuits and devices into half-micron and beyond”, Proc. Symp. VLSI circuits, pp.39–42, 1991.

    Google Scholar 

  5. J. Borel, “LP/LV circuits in the deep submicron era” in the Proceedings of the 2nd IEEE-CAS Region 8 Workshop on Analog an Mixed IC Design, Baveno, Italy, 1997.

    Google Scholar 

  6. M.A. Cirit, “Estimating dynamic power consumption of CMOS circuits”, Proc. IEEE Int. Conf. Computer Aided Design, pp.534–537, Nov. 1987.

    Google Scholar 

  7. S.R. Powell and P. Chan, “Estimating power dissipation of VLSI signal processing chips: The PFA technique”, VLSI Signal Processing IV, New-York: IEEE Press, 1990, Chapter 24.

    Google Scholar 

  8. H.J.M. Veendrick, “Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits”, vol. Sc-19, pp. 468–473, Aug. 1984.

    Google Scholar 

  9. B. Nadel, “The Green Machine”, PC Magazine, vol.12, no.10, pp.110, May, 1993.

    Google Scholar 

  10. J. Borel, “ESSCIRC’ 97 low-power, low-voltage workshop”, Southampton, UK, Sept. 1997.

    Google Scholar 

  11. J. Rapeli, “Requirements and opportunities for integrated circuit technologies for mobile communications” invited paper at the “5th IEEE International Conference on Electronics Circuits and Systems ICECS’ 98”.

    Google Scholar 

  12. J. Borel, “LP/LV circuits in the deep submicron era” in the Proceedings of the 2nd IEEE-CAS Region 8 Workshop on Analog an Mixed IC Design, Baveno, Italy, 1997.

    Google Scholar 

  13. E. Vittoz, “Future of analog in the VLSI environment”, Proc. ISCAS’ 90, pp. 1372–1375, 1990.

    Google Scholar 

Download references

Rights and permissions

Reprints and permissions

Copyright information

© 2003 Kluwer Academic Publishers

About this chapter

Cite this chapter

(2003). Introduction. In: Power Trade-Offs and Low-Power in Analog CMOS ICs. The International Series in Engineering and Computer Science, vol 662. Springer, Boston, MA. https://doi.org/10.1007/0-306-48140-5_1

Download citation

  • DOI: https://doi.org/10.1007/0-306-48140-5_1

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-0-7923-7642-2

  • Online ISBN: 978-0-306-48140-6

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics