6.6 Summary
After a brief introduction to the top-down design and bottom-up verification methodology, this chapter has presented the necessary models for the systematic design of a frequency synthesizer used in telecommunication applications. The models are tuned towards the evaluation of the trade-off between the loop settling time and phase noise performance at the output node. Both models for top-down design and bottom-up verification were presented. The validity of these models was illustrated using a 1.8 GHz CMOS frequency synthesizer.
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De Smedt, B., Gielen, G. (2001). Models and Analysis Techniques for Systematic Design and Verification of Frequency Synthesizers. In: Wambacq, P., Gielen, G., Gerrits, J., van Leuken, R., de Graaf, A., Nouta, R. (eds) Low-Power Design Techniques and CAD Tools for Analog and RF Integrated Circuits. Springer, Boston, MA. https://doi.org/10.1007/0-306-48089-1_6
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DOI: https://doi.org/10.1007/0-306-48089-1_6
Publisher Name: Springer, Boston, MA
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