Summary
In this chapter, several high-speed ADC architectures are briefly reviewed, among which pipeline ADC is most suitable for low-power high-speed medium-to-high resolution applications. Several design issues of pipeline ADCs are then discussed, with the focus on the power optimization techniques. A novel technique named dynamic biasing is proposed to reduce the total power consumption of pipeline ADCs by dynamically adjusting the biasing current of amplifiers.
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© 2002 Kluwer Academic Publishers
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(2002). Low Power ADC Design. In: Data Converters for Wireless Standards. The International Series in Engineering and Computer Science, vol 658. Springer, Boston, MA. https://doi.org/10.1007/0-306-48006-9_3
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DOI: https://doi.org/10.1007/0-306-48006-9_3
Publisher Name: Springer, Boston, MA
Print ISBN: 978-0-7923-7623-1
Online ISBN: 978-0-306-48006-5
eBook Packages: Springer Book Archive