Memory Patterns

Summary

Numerous patterns have been described in this chapter and numerous more have been developed over the years. The key is utilizing the best patterns to detect memory defects. Since it is essential that faulty memories be identified to prevent them from being shipped to the customer, thorough testing must be employed. The wrong patterns will allow bad chips to pass test.

The patterns described in this chapter do not cover all possible memory topologies. New memory configurations are generated each year as can be seen at any circuit design conference. The key is understanding fault modeling and the pattern sets described here. With a thorough examination of the specific transistor configurations utilized in the memory of concern, the appropriate fault models can be selected and the proper patterns generated. Patterns should not be considered a menu to choose from but rather a starting point for developing the correct pattern for a given memory.

Appendix B includes further patterns that can be examined for reference. Some are theoretically interesting while others can provide very helpful insight. Tables 9-16 and 9-17 describe the key factors in memory test patterns and the primary nomenclature, respectively.

“Afriendly eye could never see such faults.”