Summary
Silicon-on-insulator technology creates many interesting challenges in memory design and test. It is key to understand and factor in the parasitic bipolar and history effects inherent to memories in SOI. There are greater challenges due to increased loading along a bit line as a function of the data type stored in the cells along a column. The impact of history on cell stability must be considered as well. With careful design and test, performance advantages can be gained and robust circuitry can be implemented in silicon-on-insulator technology.
“...was to him but a memory of loveliness in far days and of his first grief⃜”
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© 2003 Kluwer Academic Publishers
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(2003). Silicon On Insulator Memories. In: High Performance Memory Testing: Design Principles, Fault Modeling and Self-Test. Frontiers in Electronic Testing, vol 22A. Springer, Boston, MA. https://doi.org/10.1007/0-306-47972-9_4
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DOI: https://doi.org/10.1007/0-306-47972-9_4
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4020-7255-0
Online ISBN: 978-0-306-47972-4
eBook Packages: Springer Book Archive