Summary
Popular solutions as well as recent innovations are presented for the solution of the combined gate and interconnect system. The impact of crosstalk noise was also explored and methodologies were proposed to measure the delay and noise impact under a static timing analysis context. The reader should be warned that the gate delay modeling remains an ongoing research problem and may continue to evolve as new technologies emerge.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
R. B. Hitchcock, G. L. Smith, and D. D. Cheng, “Timing analysis of computer hardware,” IBM Journal of Research and Development, vol. 26(1), pp. 100–105, January 1982.
N. H. E. Weste and K. Eshraghian, Principles of CMOS VLSI Design, Second Edition. Reading, MA: Addison-Wesley, pp. 213, 1992.
M. A. Horowitz, Timing Models for MOS Circuits. Ph. D. thesis, Stanford University, january 1984.
N. Jouppi, “Timing analysis and performance improvement of MOS VLSI designs,” IEEE Trans. on Computer-Aided Design, vol. CAD-6, pp. 650–665, 1987.
J. K. Ousterhout, “A switch-level timing verifier for digital MOS VLSI,” IEEE Trans. on Computer-Aided Design, vol. CAD-4, pp. 336–349, 1985.
J. Qian, S. Pullela, and L. T. Pileggi, “Modeling the effective capacitance for the RC interconnect of CMOS gates,” IEEE Trans. on Computer-Aided Design, vol. 13,no. 12, pp. 1526–1535, Dec. 1994
R.E. Mains, T. A. Mosher, L.P.P.P. van Ginneken, and R.F. Damiano, “Timing verification and optimization for the PowerPC processor family,” in Proc. Intl. Conf. on Computer Design, pp. 390–393, 1994.
F. Dartu, N. Menezes, J. Qian, and L. T. Pillage, “A gate-delay model for high-speed CMOS circuits,” in Proc. 31st ACM/IEEE Design Automation Conference, pp. 576–580, 1994.
F. Dartu, N. Menezes, and L. T. Pileggi, “Performance computation for precharacterized CMOS gates with RC loads,” IEEE Trans. on Computer-Aided Design, vol. 15,no. 5, pp. 544–553, May 1996.
J. E. Bracken, “Passive modeling for linear interconnect networks,” Technical Report, Dept. of ECE, Carnegie Mellon University, 1995.
P. R. O’Brien and T. L. Savarino, “Modeling the driving point characteristic of resistive interconnect for accurate delay estimation,” in Proc. Int. Conf. Computer-Aided Design, Nov. 1989.
R. Arunachalam, F. Dartu, and L. T. Pileggi, “CMOS gate delay models for general RLC loading,” in Proc. International Conference on Computer Design, 1997.
G. Yee, R. Chandra, V. Ganesan, and C. Sechen, “Wire delay in the presence of crosstalk,” In Proceedings of the TAU Workshop on Timing in Digital Systems, December, 1997.
P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, Third Edition. Wiley Publishers, 1992.
F. Dartu and L. T. Pileggi, “Calculating worst-case gate delay due to dominant capacitance coupling”, in Proc. IEEE/ACM Design Automation Conf., 1997.
G. H. Golub and C. F. Van Loan, Matrix Computations, Third Edition. Baltimore: The Johns Hopkins University Press. 1996.
Rights and permissions
Copyright information
© 2002 Kluwer Academic Publishers
About this chapter
Cite this chapter
(2002). Interfacing Interconnect and Gate-Delay Models. In: IC Interconnect Analysis. Springer, Boston, MA. https://doi.org/10.1007/0-306-47971-0_8
Download citation
DOI: https://doi.org/10.1007/0-306-47971-0_8
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4020-7075-4
Online ISBN: 978-0-306-47971-7
eBook Packages: Springer Book Archive