Abstract
ΔΣ converters are suitable to implement high-performance analog-to-digital converters. Several topologies are first reviewed in the context of high-resolution high-speed design targets. The remainder of the paper focuses on the influence of several important circuit non-idealities which can become performance limiting factors. A 16-bit 2.5 MS/s converter is discussed as a design example.
Yves Geerts was at KU Leuven until august 2001. Since then he has been with Alcatel Microelectronics
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© 2002 Kluwer Academic Publishers
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Geerts, Y., Steyaert, M., Sansen, W. (2002). Circuit Design Aspects of Multi-Bit Delta-Sigma Converters. In: Steyaert, M., van Roermund, A., Huijsing, J.H. (eds) Analog Circuit Design. Springer, Boston, MA. https://doi.org/10.1007/0-306-47951-6_9
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DOI: https://doi.org/10.1007/0-306-47951-6_9
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