Abstract
Early generations of analog synthesis tools failed to migrate into mainstream use primarily because of difficulties in reconciling the simplified models required for synthesis with the industrial-strength simulation environments required for validation. We have recently seen the emergence of simulation-based synthesis tools that can size/bias a fixed circuit topology by exploiting the same simulation environment created to validate the sized circuit. These methods work remarkably well across a range of difficult analog circuits, and augmented with suitable macromodeling, have also been applied successfully to system-level designs. In this paper we review the motivation and architecture of simulation-based analog synthesis tools, and survey a few recent results from industrial designs.
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References
E. Ochotta, R.A. Rutenbar, L.R. Carley, “Synthesis of High-Performance Analog Circuits and ASTRX/OBLX,” IEEE Trans. CAD, vol. 15, no. 3, Mar. 1996.
M. Krasnicki, R. Phelps, R. A. Rutenbar, L.R. Carley, “MAELSTROM: Efficient Simulation-Based Synthesis for Custom Analog Cells,” Proc. ACM/IEEE DAC, June 1999.
R. Phelps, M. Krasnicki, R.A. Rutenbar, L.R. Carley, J.R. Hellums, “ANA-CONDA: Robust Synthesis of Analog Circuits Via Stochastic Pattern Search,” Proc. IEEE Custom Integrated Circuits Conference, May 1999.
R. Phelps, M. Krasnicki, R.A. Rutenbar, L.R. Carley, J. Hellums, “A case study of synthesis for industrial-scale analog IP: Redesign of the equalizer/filter frontend for an ADSL CODEC,” Proc. ACM/IEEE DAC, June 2000.
R. Phelps, M. Krasnicki, R. A. Rutenbar, L. R. Carley, J. R. Hellums, “Anaconda: Simulation-based synthesis of analog circuits via stochastic pattern search,” IEEE Trans. CAD, vol. 19, no. 6, June 2000.
P. J. Vancorenland, G. Van der Plas, M. Steyaert, G. Gielen, and W. Sansen, “A Layout-aware Synthesis Methodology for RF Circuits”, Proc. ACM/IEEE ICCAD, Nov 2001.
P. Vancorenland, C. De Ranter, M. Steyaert, G. Gielen, “Optimal RF Design Using Smart Evolutionary Algorithms,” Proc. ACM/IEEE DAC, June 2000.
R. Schwenker, J. Eckmueller, H. Graeb, K. Antriech, “Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints,” Proc DATE99, March 1999. vol. 19, no. 6, June 2000.
M.J. Krasnicki, R. Phelps, J.R. Hellums, R.A. Rutenbar, L.R. Carley, “ASF: A Practical Simulation-Based Methodology for the Synthesis of Custom Analog Circuits,” Proc. ACM.IEEE ICC AD, Nov. 2001.
S. Dugalleix, F. Lemery, A. Shah, “Technology migration of a high-performance CMOS amplifier using an automated front-to-back analog design flow,” Proc Design Auto. & Test in Europe (DATE), March 2002.
E. Hennig, R. Sommer, L. Charlack, “An automated approach for sizing complex analog circuits in a simulation-based flow,” Proc Design Auto. & Test in Europe (DATE), March 2002.
T. McConaghy, “Intelligent Systems Solutions for Analog Synthesis,” Integrated Communications Design, Penwell, January, 2002.
E. Ochotta, T. Mukherjee, R.A. Rutenbar, L.R. Carley, Practical Synthesis of High-Performance Analog Circuits, Kluwer Academic Publishers, 1998.
G.G.E. Gielen and R.A. Rutenbar, “Computer-Aided Design of Analog and Mixed-Signal Integrated Circuits, Proc IEEE, vol. 88, no. 12, Dec. 2000.
M. Degrauwe et al., “Towards an analog system design environment,” IEEE JSSC, vol. sc-24, no. 3, June 1989.
H.Y. Koh, C.H. Sequin, and P.R. Gray, “OPASYN: a compiler for MOS operational amplifiers,” IEEE Trans. CAD, vol. 9, no. 2, Feb. 1990.
G. Gielen, et al, “Analog circuit design optimization based on symbolic simulation and simulated annealing,” IEEE JSSC, vol. 25, June 1990.
F. Leyn, W. Daems, G. Gielen, W. Sansen, “A Behavioral Signal Path Modeling Methodology for Qualitative Insight in and Efficient Sizing of CMOS Opamps,” Proc. ACM/IEEE ICCAD, 1997.
P. C. Maulik, L. R. Carley, and R. A. Rutenbar, “Integer Programming Based Topology Selection of Cell Level Analog Circuits,” IEEE Trans. CAD, vol. 14, no. 4, April 1995.
W. Kruiskamp and D. Leenaerts, “DARWIN: CMOS Opamp Synthesis by Means of a Genetic Algorithm,” Proc. 32nd ACM/IEEE DAC, 1995.
R. Harjani, R.A. Rutenbar and L.R. Carley, “OASYS: a framework for analog circuit synthesis,” IEEE Trans. CAD, vol. 8, no. 12, Dec. 1989.
B.J. Sheu, et al., “A Knowledge-Based Approach to Analog IC Design,” IEEE Trans. Circuits and Systems, CAS-35(2):256–258, 1988.
E. Berkcan, et al., “Analog Compilation Based on Successive Decompositions,” Proc. of the 25th IEEE DAC, pp. 369–375, 1988.
J. P. Harvey, et al., “STAIC: An Interactive Framework for Synthesizing CMOS and BiCMOS Analog Circuits,” IEEE Trans. CAD, Nov. 1992.
C. Makris and C. Toumazou, “Analog IC Design Automation Part II—Automated Circuit Correction by Qualitative Reasoning,” IEEE Trans. CAD, vol. 14, no. 2, Feb. 1995.
A. Torralba, J. Chavez and L. Franquelo, “FASY: A Fuzzy-Logic Based Tool for Analog Synthesis,” IEEE Trans. CAD, vol. 15, no. 7, July 1996.
M. Hershenson, S. Boyd, T. Lee, “GPCAD: a Tool for CMOS Op-Amp Synthesis”, Proc. ACM/IEEE ICCAD, pp. 296–303, 1998.
G. Gielen, P. Wambacq, and W. Sansen, “Symbolic ANalysis Methods and Applications for Analog Circuits: A Tutorial Overview,” Proc. IEEE, vol. 82, no. 2, Feb., 1990.
C.J. Shi, X. Tan, “Symbolic Analysis of Large Analog Circuits with Determinant Decision Diagrams,” Proc. ACM/IEEE ICCAD, 1997.
Q. Yu and C. Sechen, “A Unified Approach to the Approximate Symbolic Analysis of Large Analog Integrated Circuits,” IEEE Trans. Circuits and Sys., vol. 43, no. 8, August 1996.
F. Medeiro, F.V. Fernandez, R. Dominguez-Castro and A. Rodriguez-Vasquez, “A Statistical Optimization Based Approach for Automated Sizing of Analog Cells,” Proc. ACM/IEEE ICCAD, 1994.
Y-C Ju, V.B. Rao and R. Saleh, “Consistency Checking and Optimization of Macromodels”, IEEE Transactions on CAD, August 1991.
B. Antao and A. Brodersen, “ARCHGEN: Automated Synthesis of Analog Systems”, IEEE Transaction on VLSI Systems, June 1995.
F. Medeiro, B. Pérez-Verdú, A. Rodríguez-Vázquez, J. Huertas, “A vertically-integrated tool for automated design of SD modulators,” IEEE Journal of Solid-State Circuits, Vol. 30, No. 7, pp. 762–772, July 1995.
A. Doboli, et al, “Behavioral synthesis of analog systems using two-layered design space exploration,” Proc. ACM/IEEE DAC, June 1999.
W. Nye, et al, “DELIGHT.SPICE: an optimization-based system for the design of integrated circuits,” IEEE Trans. CAD, vol. 7, April 1988.
A.R. Conn, R.A. Haud, C. Viswesvariah, C.W. Wu, “Circuit optimization via adjoint lagrangians,” Proc. ACM/IEEE ICCAD, Nov. 1997.
R. Hester, et al., “CODEC for Echo-Canceling, Full-Rate ADSL Modems,” IEEE Inťl Solid-state Circuits Conference, pages 242–243. 1999.
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Rutenbar, R.A. (2002). Structured Simulation-Based Analog Design Synthesis. In: Steyaert, M., van Roermund, A., Huijsing, J.H. (eds) Analog Circuit Design. Springer, Boston, MA. https://doi.org/10.1007/0-306-47951-6_5
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DOI: https://doi.org/10.1007/0-306-47951-6_5
Publisher Name: Springer, Boston, MA
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