Summary
This paper describes a 10b DAC implemented in 0.6 μm CMOS, which converts at rates up to 400 MS/s. The DAC and associated circuits occupy 1.2 mm2. DNL is less than 0.25 LSB and INL less than 0.35 LSB. The DAC consumes 95 mW total from 3.3V, of which 25 mW is in the buffer op amp. This DAC’s unique feature is its relatively flat SFDR over the full Nyquist range of synthesized frequencies. At conversion rates beyond 100 MHz, op amp dynamics limit peak SFDR.
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Khanoyan, K., Behbahani, F., Abidi, A.A. (2003). A 400-MHz, 10-bit Charge Domain CMOS D/A Converter for Low-Spurious Frequency Synthesis. In: Huijsing, J.H., Steyaert, M., van Roermund, A. (eds) Analog Circuit Design. Springer, Boston, MA. https://doi.org/10.1007/0-306-47950-8_12
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DOI: https://doi.org/10.1007/0-306-47950-8_12
Publisher Name: Springer, Boston, MA
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