Conclusion
In this chapter we considered the impact of process variability on circuit performance, and reviewed in detail a number of effects and methods that ASIC designers can use to better understand and design chips. Intra-chip variation of process parameters is increasing as a portion of the overall variation, as well as in absolute terms. Intra-chip variation significantly degrades the distribution of the achievable clock speed. At the same time, it makes the timing estimates provided by the standard design methodology overly conservative. ASIC circuits suffer more from this effect than do custom circuits. This is because the lack of at-speed testing for ASICs does not permit even the least parametric yield loss. As a result, ASIC designers are forced to use extremely conservative lumped worst-case models that assume a simultaneous set of all the worst-case parameters, both physical (e.g. process-related) and environmental (temperature, V DD ). Fundamentally, as long as ASIC designers cannot tolerate any parametric yield loss, they will have to live with the fact that the same design may have run, on average, 20–30% faster, and sometimes, 40–50% faster.
Still, ASIC designers may win back some performance through improved delay modeling using techniques indicated in this chapter. While these techniques are not currently commercially available, it seems likely that statistical information will eventually be integrated into commercial timing tools and made available to ASIC designers.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
Ajami, A., Banerjee, K., and Pedram, M., “Analysis of Substrate Thermal Gradient Effects on Optimal Buffer Insertion,” Proc. of IEEE/ACM International Conference on Computer Aided Design, p. 44, 2001.
Bernstein, K., et al., High Speed CMOS Design Style, Kluwer Academic Publishing, 1998.
Bolt, M., Rocchi, M., and Angel, J., “Realistic Statistical Worst-Case Simulations of VLSI Circuits,” Trans. on Semicon. Manufacturing, n.3, pp.193–198, 1991.
Boning, D., and Nassif, S., “Models of Process Variations in Device and Interconnect,” in Design of High-Performance Microprocessor Circuits, A. Chandrakasan (ed.), 2000.
Bowman, K., and Meindl, J., “Impact of within-die parameter fluctuations on the future maximum clock frequency distribution,” Proc. of CICC, 2001.
Bowman, K., Duvall, S., and Meindl, J., “Impact of within-die and die-to-die parameter fluctuations on maximum clock frequency,” Proc. of ISSCC, 2001.
Brglez, F., and Fujiwara, H., “A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortran,” distributed on a tape to participants of the Special Session on ATPG and Fault Simulation, International Symposium on Circuits and Systems, June 1985.
Burggraaf, P., “Optical lithography to 2000 and beyond,” Solid State Technology, Feb. 1999
Burnett, D., et al., “Implications of Fundamental Threshold Voltage Variations for High-Density SRAM and Logic circuits,” Symp. VLSI Tech., pp. 15–16, Jun. 1994
Chang, E., et al., “Using a Statistical Metrology Framework to Identify Systematic and Random Sources of Die-and Wafer-levelILD Thickness Variation in CMP Processes,” Proc. of IEDM, 1995.
Chen, J., et al., “E-T Based Statistical Modeling and Compact Statistical Circuit Simulation Methodologies,” Proc. of IEDM, pp. 635–638, 1996.
Chen, K., et al., “Accurate Models for CMOS Scaling in Deep Submicron Regime,” 1997 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD’ 97), Boston, September 1997.
Chinnery, D., and Keutzer, K., “Closing the Gap Between ASICs and Custom,” Proc. of DAC, 2000.
Divecha, R. R., et al., “Effect of Fine-line Density and Pitch on Interconnect ILD Thickness Variation in Oxide CMP Process,” Proc. CMP-MIC, 1998.
Eisele, M., et al. “The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits,” Proc. of ISLPED, pp. 237–242, 1996.
Fitzgerald, D., “Analysis of polysilicon critical dimension variation for submicron CMOS processes,” M.S. thesis, Dept. Elect.Eng. Comp. Sci., Mass. Inst. Technol., Cambridge, June 1994.
Kahng, A., and Pati, Y., “Subwavelength optical lithography: challenges and impact on physical design,” Proceedings of ISPD, p.112, 1999.
Kahng, A. B., et al., “Filling Algorithms and Analyses for Layout Density Control,” IEEE Trans. Computer-Aided Design 18(4) (1999), pp.445–462.
Lenevson, M.D., Viswanathan, N. S., and Simpson, R. A. “Improving resolution in photolithography with a phase-shifting mask,” IEEE Trans. On Electron Devices, 29 (11): 1828–1836, 1982.
Liu, H., et al., “The application of alternating phase-shifting masks to 140nm gate patterning: line width control improrvements and design optimization,” Proc. of SPIE 17th annual BACUS Symposium on Photomask Technologies, volume 3236 of SPIE, 1998.
Mehrotra, V., et al. “Modeling the effects of manufacturing variation on high-speed microprocessor interconnect performance,” IEDM Technical Digest, p.767, 1998.
Mentor Graphics, Subwavelength-Compliant Cell Generation Flow, 2001. http://www.mentor.com/press_releases/feb01/prolific_calibre_pr.html
Nassif, S., “Delay Variability: Sources, Impact and Trends,” Proc. of International Solid-State Circuits Conference, 2000.
Nassif, S., “Statistical worst-case analysis for integrated circuits,” Statistical Approaches to VLSI, Elsevier Science, 1994.
Nassif, S., “Within-chip variability analysis,” IEDM Technical Digest, p.283, 1998.
Numerical Technologies, “Phase shifting technology,” 2002. http://www.numeritech.com/nttechnology
Orshansky, M., et al., “Characterization of spatial CD variability, spatial mask-level correction, and improvement of circuit performance,” Proceedings of the International Society for Optical Engineering, vol.4000, pt.1–2, 2000, 602–611.
Orshansky, M., et al., “Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits,” Proc. of IEEE/ACM International Conference on Computer Aided Design, pp. 62–27, San Jose, CA, 2000.
Orshansky, M., Spanos, C., and Hu, C., “Circuit Performance Variability Decomposition,” Proc. of 4th IEEE International Workshop on Statistical Metrology for VLSI Design and Fabrication, p.10–13, Kyoto, Japan, 1999.
Orshansky, M., and Keutzer, K., “A Probabilistic Framework for Worst Case Timing Analysis,” Proc. of DAC, 2002.
Power, J. et al., “An Approach for Relating Model Parameter Variabilities to Process Fluctuations,” Proc. ICTMS, 1993, p. 63.
Sai-Halasz, G., “Performance trends in high-end processors,” Proc. IEEE, 1995.
Semiconductor Industry Association, International Roadmap for Semiconductors, 1999.
Semiconductor Industry Association, International Technology Roadmap for Semiconductors, 2001.
Sylvester, D., Keutzer, K., “Getting to the bottom of deep-submicron,” Proceedings of the International Conference on Computer-Aided Design, 1998.
Stine, B., et al., “Inter-and intra-die polysilicon critical dimension variation,” Microelectronic Manufacturing Yield, Reliability, and Failure Analysis II, SPIE 1996 Symp. Microelectronic Manufacturing, Oct. 1996, Austin, TX.
Stine, B., Boning, D. S., and Chung, J. E., “Analysis and decomposition of spatial variation in integrated circuit processes and devices,” IEEE Trans. On Semiconductor Manufacturing, No.1, pp. 24–41, Feb. 1997
Stine, B., et al., “Simulating the Impact of Pattern-Dependent Poly-CD Variation on Circuit Performance,” IEEE Trans. on Semiconductor Manufacturing, Vol. 11, No. 4, November 1998.
Stine, B., et al., “A methodology For Assessing the Impact of Spatial/Pattern-Dependent Interconnect Variation on Circuit Performance,” Proc. of IEDM, p. 133, 1997.
Stine, B., et al., “A Closed-Form Analytic Model for ILD Thickness Variation in CMP Processes,” CMP-MIC, p. 266, 1997.
Takeuchi, K., Tatsumi, T., and Furukawa A., “Channel Engineering for the Reduction of Random-Dopant-Placement-Induced Threshold Voltage Fluctuations,” IEDM Tech. Dig., Dec. 1997
Van den hove, L., et al., “Optical lithography techniques for 0.25um and below: CD control issues,” Int. Symposium on VLSI Technology, 1995.
Wu, Q., Qiu, Q., and Pedram, M., “Dynamic power management of complex systems using generalized stochastic Petri nets,” Proc. DAC., pp. 352–356, June 2000.
Yang, P., et al., “An integrated and efficient approach for MOS VLSI statistical circuit design,” IEEE Trans. on CAD, No 1, Jan. 1986.
Yu, C., et al., “Use of short-loop electrical measurements for yield improvement,” IEEE Trans. on Semiconductor Manufacturing, vol. 8, no. 2, May 1995.
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2004 Kluwer Academic Publishers
About this chapter
Cite this chapter
Orshansky, M. (2004). Increasing Circuit Performance through Statistical Design Techniques. In: Closing the Gap Between ASIC & Custom. Springer, Boston, MA. https://doi.org/10.1007/0-306-47823-4_14
Download citation
DOI: https://doi.org/10.1007/0-306-47823-4_14
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4020-7113-3
Online ISBN: 978-0-306-47823-9
eBook Packages: Springer Book Archive