What is Verification?

Summary

In this chapter, after briefly outlining what a testbench is, I described the importance of verification. Parallelism, automation and abstractions were identified as strategies to reduce the time necessary to implement testbenches. A model was developed to illustrate and identify what exactly is being verified in any verification process. It was then applied to various verification tools and methodologies currently available and to differentiate verification from manufacturing test. Techniques for eliminating the uncertainty introduced by human intervention in the verification process were also described. The importance of verification for design reuse and the cost of verification were also discussed.