Verifiable RTL Tutorial

Summary

This chapter presented a tutorial on Verilog language elements applicable register transfer abstraction level and their verifiable use.

For verifiability, we emphasized strong typing and fully-specified state machines using case, casex and if-else statements. Since the Verilog X-state is counter-productive in RTL verification (see chapter 7), we omitted it.

We reviewed debugging statements, constant naming, code inclusion controls and command line options for compilation and simulation in a verification environment.