RTL Methodology Basics

Summary

In this chapter, we addressed the problem of complexity due to competing tool coding requirements by: (a) introducing a simplified and tool efficient Verilog RTL verifiable subset, (b) detailing a linting methodology used to enforce project specific coding rules and tool performance checks, and (c) introducing an Object-Based Hardware Design (OBHD) methodology,.

By constraining the RTL to a verifiable subset, the designer will succeed in augmenting their traditional verification process with cycle-based simulation, 2-state simulation, formal equivalence checking, and model checking. A verifiable RTL coding style allows the engineer to achieves greater verification coverage in minimal time, enhances the cooperation and support for multiple EDA tools within the flow, clarifies RTL design intent, and facilitates emerging verification processes.

By applying the principle of information hiding and developing an OBHD methodology, the designer will succeed in isolating design details within tool-specific libraries. This methodology facilitates simultaneously optimizing the performance of simulation, equivalence checking, model checking and physical design within a project’s design flow. Furthermore, an OBHD methodology allows adding new features and tools to the design flow throughout the duration of a project, without interfering with the text or functional intent of the original design.