Summary
In summary, both layout design and technology evolution will strongly influence ESD protection circuit design and performance. In terms of layout, two basic considerations should be kept in mind when doing ESD protection circuit design, i.e., to ensure uniform current distribution and to make area efficient layout. Practical ESD-enhancement layout techniques include to use smoothed geometries, to set up adequate critical spacing, to properly place contacts and vias, as well as to optimise metal interconnect routing, and so on. Use of bounding pad oriented ESD protection is a very attractive solution to high-pin-count area-sensitive chips. In regarding technological impacts, every single new process techniques designed to boost transistor operation should be evaluated against its influences on ESD protection performance. Most advanced process techniques, such as, LDD and silicidation, can degrade ESD robustness dramatically. Technology scaling generally makes ESD protection circuit design more difficult. Many after-qualification fixing measures are available to recover the lose in ESD protection performance, such as LDD-blocking, silicide-blocking and ESD implant, etc, at extra costs. It is wise to consider technology-ESD co-development in early phase of new process development, where it is possible to strike a balance between regular transistor operation and ESD robustness. In near future, ESD protection for VDSM and nano-scale technologies is a challenge to be addressed.
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Wang, A.Z.H. (2002). Layout and Technology Influences on ESD Protection Circuit Design. In: On-Chip ESD Protection for Integrated Circuits. The International Series in Engineering and Computer Science, vol 663. Springer, Boston, MA. https://doi.org/10.1007/0-306-47618-5_7
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DOI: https://doi.org/10.1007/0-306-47618-5_7
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