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References

  1. Rountree, R. and Hutchins, C., “NMOS Protection Circuitry”, IEEE Trans. Elec. Dev., ED-32, 1985, pp.910–917.

    Article  Google Scholar 

  2. Duvvury, C., Taylor, T., Lindgren, J., and Kumar, S., “Input Protection Design for Overall Chip Reliability”, Proc. EOS/ESD Symp., 1989, pp.190–198.

    Google Scholar 

  3. Hulett, T., “On Chip Protection of High Density NMOS Devices”, Proc. EOS/ESD Symp., 1981, pp.90.

    Google Scholar 

  4. Amerasekera, A. and Duvvury, C., ESD in Silicon Integrated Circuits, New York, Wiley, 1995.

    Google Scholar 

  5. Scott, D., Giles, G., and Hall, J., “A Lumped Element Model for Simulation of ESD Failures in Silicided Devices”, Proc. EOS/ESD Symp., 1986, pp.41–47.

    Google Scholar 

  6. Chen, K.-L., “Effect of Interconnect Process and Snapback Voltage on the ESD Failure Threshold of NMOS Transistors”, Proc. EOS/ESD Symp., 1988, pp.212–219.

    Google Scholar 

  7. Polgreen, T. and Chatterjee, A., “Improving the ESD Failure Threshold of Silicided nMOS Output Transistors by Ensuring Uniform Current Flow”, Proc. EOS/ESD Symp., 1989, pp. 167–174.

    Google Scholar 

  8. Feng, H. G., “A Mixed-Mode Simulation-Design Methodology for on-Chip ESD Protection Design”, MS Thesis, May, 2001.

    Google Scholar 

  9. Kamata, T., Tanabashi, K., and Kobayashi, K, “Substrate Current due to Impact Ionization in MOSFET”, Jpn J. Appl. Phys., 15, 1976, pp.1127.

    Article  Google Scholar 

  10. Sze, S. M., Physics of Semiconductor Devices, 2 nd Ed., Wiley, New York, 1981.

    Google Scholar 

  11. Toriumi, A, “Experimental Study of Hot Carriers in Small Size Si-MOSFETs” Solid State Electron., 32(12), 1989, pp. 1519–1525.

    Article  Google Scholar 

  12. Tam, S., Ko, P., and Hu, C., “Lucky-Electron Model of Channel Electron Injection in MOSFET’s”, IEEE Trans. Elec. Dev., ED-31(9), 1984, pp.1116.

    Google Scholar 

  13. Tam, S and Hu, C., “Hot-Electron-Induced Photon and Photocarrier Generation in Silicon MOSFET’s”, IEEE Trans. Elec. Dev. ED-31(9), 1984, pp. 1264.

    Article  Google Scholar 

  14. Fischetti, M, Laux, S. and Crabbe, E., “Understanding Hot-Electron Transport in Silicon Devices: is there a Short Cut?” J. Appl. Phys., 1995, pp.1058.

    Google Scholar 

  15. Chan, T. Y., Ko, P. K., and Hu, C., “A Simple Method to Characterize Substrate Current in MOSFETs”, IEEE Elec. Dev. Letts, EDL-5, December 1984, pp.505.

    Google Scholar 

  16. Hu, C., “Hot-Carrier Effects”, Chapter 3, Advanced MOS Device Physics, Einspruch, N. G., and Gildenblat, G., Eds, Vol. 18, VLSI Electronics Microstructure Science, Academic Press, San Diego, CA, 1989, pp. 119–160.

    Chapter  Google Scholar 

  17. Duvvury, C. and Diaz, C., “Dynamic Gate-Coupled NMOS for Efficient Output ESD Protection”, Proc. Int. Rel. Phys. Symp., 1992, pp.141–150.

    Google Scholar 

  18. Krakauer, D. and Mistry, K, “Circuit Interactions during Electrostatic Discharge”, Proc. EOS/ESD Symp., 1994, pp. 113–119.

    Google Scholar 

  19. Corsi, M., Nimmo, R. and Fattori, F., “ESD Protection of BiCMOS Integrated Circuits Which Need to Operate in the Harsh Environments of Automotive or Industrial”, Proc. EOS/ESD Symp., 1993, pp.209–213.

    Google Scholar 

  20. Mack, W. and Meyer, R., “New ESD Protection Schemes for BiCMOS Processes with Application to Cellular Radio Designs”, Proc. IEEE. 0_7803_0593_0, 1992, pp.2699–2702.

    Google Scholar 

  21. Tandan, N., “ESD Trigger Circuit”, Proc. EOS/ESD Symp., 1994, pp.120–124.

    Google Scholar 

  22. Smith, J., “A Substrate Triggered Lateral Bipolar Circuit for High Voltage Tolerant ESD Protection Applications”, Proc. EOS/ESD Symp., 1998, pp.63–71.

    Google Scholar 

  23. Chatterjee, A. and Polgreen, T., “A Low_Voltage Triggering SCR for on_Chip ESD Protection at Output and Input Pads”, IEEE Elec. Dev. Letts., Vol. 12, No., 1, January 1991, pp.21–22.

    Article  Google Scholar 

  24. Duvvury, C. and Amerasekera, A., “Advanced CMOS Protection Device Trigger Mechanisms During CDM”, Proc. EOS/ESD Symp., 1995, pp.162–174.

    Google Scholar 

  25. Ker, M., Chang, H. and Wu, C., “A Gate_Coupled PTLSCR/NTLSCR ESD Protection Circuit for Deep_Submicron Low_Voltage CMOS IC’s”, IEEE J. Solid_State Cir., Vol. 32, No. 1, January 1997, pp.38–50.

    Article  Google Scholar 

  26. Chen, J. Amerasekera, A. and Vrotsos, T., “Bipolar SCR ESD Protection Circuit for High Speed Submicron Bipolar/ BiCMOS Circuits”, IEEE IEDM Digest, 1995, pp. 337–340.

    Google Scholar 

  27. Ker, M., “Lateral SCR Devices with Low_Voltage High_Current Triggering Characteristics for Output ESD Protection in Submicron CMOS Technology”, IEEE Trans. Elec. Dev., Vol., 45, No. 4, April 1998, pp.849–860.

    Article  Google Scholar 

  28. Carbajal, B., Cline, R. and Anderson, B, “A Successful HBM ESD Protection Circuit for Micron and Sub_Micron Level CMOS”, Proc. EOS/ESD Symp., 1992, pp.234–242.

    Google Scholar 

  29. Voldman, S., Gross, V., Hargrove, M., Never, J., Slinkman, A., O’Boyle, M., Scott, S and Delecki, J., “Shallow Trench Isolation Double_Diode Electrostatic Discharge Circuit and Integration with DRAM Output Circuitry”, Proc. EOS/ESD Symp., 1992, pp. 277–288.

    Google Scholar 

  30. Ker, M., Wang, K., Joe M., Chu, Y. and Wu, T., “Area_Efficient CMOS Output Buffer with Enhanced High ESD Reliability for Deep Submicron CMOE ASIC”, Proc. IEEE Int. ASIC Conf., 1995, pp.123–126.

    Google Scholar 

  31. Wu, C. and Ker, M., “ESD Protection for Output Pad with Well-Coupled Field_Oxide Device in 0.5μm CMOS Technology”, IEEE Trans. Elec. Dev., Vol. 44, No. 3, March 1997, pp.503–505.

    Article  Google Scholar 

  32. Chan, T. and Culver, D, “ESD Protection Circuit”, U.S. Patent, No. 5,329,143, 1994.

    Google Scholar 

  33. Scott, D, Bosshart, P and Gallia, J, “Circuit to Improve Electrostatic Discharge Protection”, U.S. Patent, No. 5,019,888, 1991.

    Google Scholar 

  34. Voldman, S., Gerosa, G., Gross, V., Dickson, N., Furkey, S. and Slinkman, J., “Analysis of Snubber_Clamped Diode_String Mixed Voltage Interface ESD Protection Network for Advanced Microprocessors”, J. Electrostatics, Elsevier Science, 38, 1996, pp.3–31.

    Article  Google Scholar 

  35. Dabral., S. and Maloney, T., “Designing on-Chip Power Supply Coupling Diodes for ESD Protection and Noise Immunity”, Proc. EOS/ESD Symp., 1993, pp.239–249.

    Google Scholar 

  36. Merrill, R. and Issaq, E., “ESD Protection Methodology”, Proc. EOS/ESD Symp.. 1993, pp.233–237.

    Google Scholar 

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Wang, A.Z.H. (2002). ESD Protection Circuit Solutions. In: On-Chip ESD Protection for Integrated Circuits. The International Series in Engineering and Computer Science, vol 663. Springer, Boston, MA. https://doi.org/10.1007/0-306-47618-5_4

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  • DOI: https://doi.org/10.1007/0-306-47618-5_4

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-0-7923-7647-7

  • Online ISBN: 978-0-306-47618-1

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