Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Dangelmayer, G. T., ESD Program Management, Boston, Kluwer Academic Publishers, 1999.
Moss, R., “Caution-Electrostatic Discharge at Work”, IEEE Trans. Comp. Hyb. And Man., CHMT-5, 1982, pp. 512–515.
Van Roozendaal, L., Amerasekera, A., Bos, P., Baelde, W., Bontekoe, F., Kersten, P., Korma, E., Rommers, P., Krys, P., Weber, U., and Ashby, P., “Standard ESD Testing of Integrated Circuits”, Proc. EOS/ESD Symposium, 1990, pp. 119–130.
Amerasekera, A. and Verweij, J., “BSD in Integrated Circuits”, Quality and Reliability International, Vol. 8, 1992, pp. 259–272.
Verhaege, K., Roussel, P., Groeseneken, G., Maes, H., Gieser, H., Russ, C., Egger, P., Guggenmos, X., and Kuper, F., “Analysis of HBM ESD Testers and Specifications Using a 4th Order Lumped Element Model”, Proc. EOS/ESD Symposium, 1993, pp. 129–137.
Speakman, T., “A Model for Failure of Bipolar Silicon Integrated Circuits Subjected to Electrostatic Discharge”, Proc. IEEE Int’l Rel. Phys. Symp., 1974, pp. 60–69.
Bossard, P., Chemelli, R. and Unger, B., “ESD Damage from Triboelectrically Charged IC Pins”, Proc. EOS/ESD Symp., 1980, pp. 17–22.
Chaine, M., Verhaege, K., Avery, L., Kelly, M., Gieser, H., Bock, K., Henry, L., Meuse, T., Brodbeck, T., and Barth, J., “Investigation into Socketed CDM Tester Parasitics”, Proc. EOS/ESD Symp., 1998, pp. 301–310.
Maloney, T. and Khurana, N., “Transmission Line Pulsing Technique for Circuit Modelling of ESD Phenomena”, Proc. EOS/ESD Symp., 1985, pp. 49–54.
Barth, J., Verhaege, K., Henry, L., and Richner, J., “TLP Calibration, Correlation, Standards, and New Techniques”, Proc. EOS/ESD Symp., 2000, pp.85–96.
Stadler, W., Guggenmous, X., Egger, P., Gieser, H. and Mussshoff, C., “Does the ESD Failure Current Obtained by Transmission-Line Pulsing Always Correlate to Human Body Model Tests?” Proc. EOS/ESD Symp., 1997, pp.366–372.
Amerasekera, A., Roozendaal, L., Abderhalden, J., Bruines, J., and Sevat, L., “An Analysis of Low Voltage ESD Damage in Advanced CMOS Processes”, Proc. EOS/ESD Symp., 1990, pp. 143–150.
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2002 Kluwer Academic Publishers
About this chapter
Cite this chapter
Wang, A.Z.H. (2002). ESD Test Models. In: On-Chip ESD Protection for Integrated Circuits. The International Series in Engineering and Computer Science, vol 663. Springer, Boston, MA. https://doi.org/10.1007/0-306-47618-5_2
Download citation
DOI: https://doi.org/10.1007/0-306-47618-5_2
Publisher Name: Springer, Boston, MA
Print ISBN: 978-0-7923-7647-7
Online ISBN: 978-0-306-47618-1
eBook Packages: Springer Book Archive