Skip to main content

Part of the book series: The International Series in Engineering and Computer Science ((SECS,volume 663))

  • 837 Accesses

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 189.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 249.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 249.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Merril, R. and Issaq, E., “ESD Design Methodology”, Proc. EOS/ESD Symp., 1993, pp. 233–237.

    Google Scholar 

  2. Green, T. J. and Denson, W. K., “Review of EOS/ESD Field Failures in Military Equipment”, Proc. EOS/ESD Symp., 1988, pp. 7–14.

    Google Scholar 

  3. Dangelmayer, G. T., ESD Program Management, Boston, Kluwer Academic Publishers, 1999.

    Google Scholar 

  4. Amerasekera, A. and Duvvury, C., ESD in Silicon Integrated Circuits, New York, Wiley, 1995.

    Google Scholar 

  5. Wang, A., Tsay, C., Lele, A. and Deane, P., “A Study of NMOS Behaviour under ESD Stress: Simulation and Characterization”, Microelectronics Reliability, 38, Elsevier Science, 1998, pp.1183–1186.

    Article  Google Scholar 

  6. Chen, J., Zhang, X., Amerasekera, A. and Vrotsos, T., “Design and Layout of a High ESD Performance NPN Structure for Submicron BiCMOS/Bipolar Circuits”, Proc. EOS/ESD Symp., 1996, pp. 227–232.

    Google Scholar 

  7. Wang, A. and Tsay, C., “On a Dual-Direction on-Chip Electrostatic Discharge Protection Structure”, IEEE Trans. Elec. Devices, Vol. 48, No. 5, April 2001, pp. 978–984.

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Rights and permissions

Reprints and permissions

Copyright information

© 2002 Kluwer Academic Publishers

About this chapter

Cite this chapter

Wang, A.Z.H. (2002). Introduction. In: On-Chip ESD Protection for Integrated Circuits. The International Series in Engineering and Computer Science, vol 663. Springer, Boston, MA. https://doi.org/10.1007/0-306-47618-5_1

Download citation

  • DOI: https://doi.org/10.1007/0-306-47618-5_1

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-0-7923-7647-7

  • Online ISBN: 978-0-306-47618-1

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics