Conclusion
A 10-Gb/s clock and data recovery circuit designed in 0.18-μm CMOS technology performs frequency acquisition, phase locking, and data regeneration. Achieving an rms jitter of 0.8 ps, this circuit is the first CMOS CDR circuit to meet the jitter generation requirements defined by SONET. The power consumption of this circuit is much smaller than the power consumption of similar circuits fabricated in bipolar or GaAs processes.
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© 2002 Kluwer Academic Publishers
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(2002). A 10-Gb/s CMOS CDR Circuit with Wide Capture Range. In: High-speed CMOS Circuits for Optical Receivers. Springer, Boston, MA. https://doi.org/10.1007/0-306-47576-6_6
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DOI: https://doi.org/10.1007/0-306-47576-6_6
Publisher Name: Springer, Boston, MA
Print ISBN: 978-0-7923-7388-9
Online ISBN: 978-0-306-47576-4
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