The Time-Triggered Architecture

Overview

In the final chapter, the different concepts that have been developed in the previous thirteen chapters are brought together into a coherent time-triggered architecture (TTA). This architecture is being implemented at the Technische Universität Wien with industrial support, taking advantage of the lessons learned during the more than fifteen years of research on dependable distributed real-time systems.

The chapter starts with a short description of the MARS (MAintainable Real-time System) project. It then gives an overview of the time-triggered architecture (TTA) and emphasizes the essential role of the real-time database in this architecture. The building blocks of a TTA prototype implementation are described. The only nonstandard hardware unit is the TTP/C communication controller. The TTP/C controller implements all functions of the TTP/C protocol and interfaces to the host via a dualported memory. The TTP controller contains independent bus guardians to protect the bus against “babbling idiot” failures of the nodes.

Section 14.3 is devoted to the software support tools that are being implemented and planned for the development of software in the TTA. The time-triggered operating system that has been developed for MARS has been ported to the TTA host, and adapted to the Communication Network Interface of the TTP controller. The generation of the message descriptor lists for the TTP controller is supported by a “cluster compiler”. The fault-tolerance strategy of the TTA is covered in Section 14.4. TTA supports the implementation of replicated communication channels and fault-tolerant units consisting of replicated fail-silent nodes, TMR nodes, and other FTU organizations.

Finally. Section 14.5 speculates on the implementation of TTA systems that are dispersed over a wide geographical area.