Advertisement

Realization of Efficient Architectures for Digital Filters: A Survey

  • Prashant KumarEmail author
  • Prabhat Chandra Shrivastava
  • Manish Tiwari
  • Amit Dhawan
Conference paper
First Online:
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 587)

Abstract

Digital filters are considered as one of the most important parts of signal processing. Due to lots of advancements in VLSI designs, the dedicated hardware design for the 2-D digital filters snatched the attention of researchers. This paper briefly discusses the challenges of 2-D digital filter’s architecture designs and presents the review on suggested methodologies and efficient architectures for 2-D digital filters. A discussion on architectures for separable 2-D digital filters is also presented. In many applications, the frequency response of digital filters poses certain symmetries and due to that, the dedicated architectures require a lesser number of multipliers. So, the suggested architectures for these filters are discussed in this paper. Furthermore, a short review of architectures for 2-D block processing is also given. Moreover, this paper also presents the comparative analysis of hardware and time complexities of all suggested architectures..

Keywords

2-D digital filter Systolic architecture Symmetries in digital filters Block filtering 
This is a preview of subscription content, log in to check access.

References

  1. 1.
    Sid-Ahmed, M.A.: Image Processing: Theory, Algorithms, and Architectures. McGraw-Hill, NY (1995)Google Scholar
  2. 2.
    Dudgeon, D.E., Mersereau, R.M.: Multidimensional Digital Signal Processing. Prentice-Hall, Englewood Cliffs, NJ (1984). Chap. 4Google Scholar
  3. 3.
    Joshi, R.M., Madanayake, A., Adikari, J., Bruton, L.T.: Synthesis and array processor realization of a 2-D IIR beam filter for wireless applications. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 20(12), 2241–2254 (2012)CrossRefGoogle Scholar
  4. 4.
    Swamy, M.N.S., Rajan, P.K.: Symmetry in 2-D Filters and Its Application, Multidimensional Systems: Techniques and Applications (S.G. Tzafestas, Ed.). Marcel Dekkar, New York (1986). Chap. 9Google Scholar
  5. 5.
    Wijenayake, C.K., Madanayake, A., Bruton, L.T.: FPGA prototypes of differential-form 2D-IIR systolic-array DSP architectures for multi-beam plane-wave filters In: Proceedings IEEE SIPS, pp. 58–63. San Francisco, CA (2010)Google Scholar
  6. 6.
    Tekalp, A.M.: Digital Video Processing. Prentice-Hall, Englewood Cliffs, NJ (1995). Chap. 14Google Scholar
  7. 7.
    Gnanasekaran, R.: 2-D filter implementations for real-time signal processing. IEEE Trans. Circuits Syst. 35(5), 587–590 (1988)MathSciNetCrossRefGoogle Scholar
  8. 8.
    Mitra, S.K., Sagar, A.D., Pendergrass, N.A.: Realization of two dimensional recursive digital filters. IEEE Trans. Circuits Syst. 22, 171–184 (1975)CrossRefGoogle Scholar
  9. 9.
    Zhang, H., Yuan, B.: A new VLSI structure for 2-D FIR digital filters. In: IEEE 9th Annual Conference on Proceedings of TENCON’94. ‘Frontiers of Computer Technology’, vol. 1, pp. 534–536. Singapore (1994)Google Scholar
  10. 10.
    Venetsanopoulos, A., Mertzios, B.: High-speed architectures for digital image processing. IEEE Trans. Circuits Syst. 34(8), 887–896 (1987)CrossRefGoogle Scholar
  11. 11.
    Sid-Ahmed, M.A.: A systolic realization for 2-D digital filters. IEEE Trans. Acoust. Speech Signal Process. ASSP-37(4), 560–565 (1989)CrossRefGoogle Scholar
  12. 12.
    Sunder, S., El-Guibaly, F., Antoniou, A.: Systolic implementations of two-dimensional recursive digital filters. In Proceedings IEEE International Symposium Circuits System, pp. 1034–1037 (1990)Google Scholar
  13. 13.
    Shanbhag, N.R.: An improved systolic architecture for 2-D digital filters. IEEE Trans. Signal Process. 39, 1195–1202 (1991)CrossRefGoogle Scholar
  14. 14.
    Van, L.D., Tang, C.C., Tenqchen, S., Feng, W.S.: A new VLSI architecture without global broadcast for 2-D systolic digital filters. In: IEEE International Symposium Circuits System, vol. 1, pp. 547–550. Geneva, Switzerland (2000)Google Scholar
  15. 15.
    Van, L.D., Tenqchen, S., Chang, C.H., Feng, W.S.: A new2-D digital filter using a locally broadcast scheme and its cascade form. In: IEEE Asia Pacific Conference on Circuits System, pp. 579–582. Tianjin, China (2000)Google Scholar
  16. 16.
    Van, L.D.: A new 2-D systolic digital filter architecture without global broadcast. IEEE Trans. VLSI Syst. 10(4), 477–486 (2002)CrossRefGoogle Scholar
  17. 17.
    Khoo, I.H., Reddy, H.C., Van, L.D., Lin, C.T.: 2-D digital filter architectures without global broadcast and some symmetry applications. In: IEEE International Symposium Circuits System ISCAS, pp. 952–95 (2009)Google Scholar
  18. 18.
    Khoo, I.H., Reddy, H.C., Van, L.D., Lin, C.T.: Generalized formulation of 2-D filter structures without global broadcast for VLSI implementation. In: IEEE MWSCAS, pp. 426–429 (2010)Google Scholar
  19. 19.
    Mohanty, B.K., Meher, P.K.: New scan method and pipeline architecture for VLSI implementation of separable 2-D FIR filters without using transposition. In: Proceedings of IEEE Region 10 TENCON 2008 Conference. Hyderabad, India (2008)Google Scholar
  20. 20.
    Reddy, H.C., Khoo, I.H., Rajan, P.K.: 2-D symmetry: theory and filter design applications. IEEE Circuits Syst. Mag. 3, 4–33 (2003)CrossRefGoogle Scholar
  21. 21.
    Chen, P.Y., Van, L.D., Reddy, H.C., Lin, C.T.: A new VLSI 2-D diagonal-symmetry filter architecture design. In: Proceedings of IEEE APCCAS, pp. 320–323. Macao, China (2008)Google Scholar
  22. 22.
    Chen, P.Y., Van, L.D., Reddy, H.C., Lin, C.T.: A new VLSI 2-D fourfold-rotational-symmetry filter architecture design. In: Proceeding IEEE International Symposium on Circuits System (ISCAS), pp. 93–96 (2009)Google Scholar
  23. 23.
    Chen, P.Y., Van, L.D., Khoo, I.H., Reddy, H.C., Lin, C.T.: Power efficient cost-effective 2-D symmetry filter architecture. IEEE Trans. Circuit Syst. I, Reg. Papers 58(1), 112–125 (2011)Google Scholar
  24. 24.
    Chen, P.Y., Van, L.D., Reddy, H.C., Khoo, I.H.: Area-efficient 2-D digital filter architectures possessing diagonal and four-fold rotational symmetries. In: Proceedings of ICICS. Taiwan (2013)Google Scholar
  25. 25.
    Kawan, H.: Systolic and parallel realization of 2-D IIR digital filter. In: IEEE International Symposium On Circuit and Systems, vol. 3, pp. 2345–2348. USA (1990)Google Scholar
  26. 26.
    Mohanty, B.K., Meher, P.K.: Cost-effective novel flexible cell-level systolic architecture for high throughput implementation of 2-D FIR filters. IEEE Proc. Comput. Digital Tech. 143(6), 436–439 (1996)CrossRefGoogle Scholar
  27. 27.
    Mohanty, B.K., Meher, P.K., Al-Maadeed, S., Amira, A.: Memory footprint reduction for power-efficient realization of 2-D finite impulse response filters. IEEE Trans. Circuits Syst. I, Reg. Papers 61(1), 120–133 (2014)CrossRefGoogle Scholar
  28. 28.
    Kumar, P., Shrivastava, P., Tiwari, M., Mishra, G.: High-throughput, area-efficient architecture of 2-D block FIR filter using distributed arithmetic algorithm. Circuits Syst. Signal Process (2018).  https://doi.org/10.1007/s00034-018-0897-2CrossRefGoogle Scholar
  29. 29.
    Kumar, P., Shrivastava, P., Tiwari, M., Dhawan, A.: ASIC implementation of area-efficient high-throughput 2-D IIR filter using distributed arithmetic. Circuits System Signal Process 37(7), 2934–2957 (2018).  https://doi.org/10.1007/s00034-017-0698-zMathSciNetCrossRefzbMATHGoogle Scholar
  30. 30.
    Weste, N.H.E, Eshraghian, K.: Principles of COMS VLSI Design: A Systems Perspective, 2nd ed. Addison-Wesley, Reading, MA (1993). Chaps. 3–5Google Scholar
  31. 31.
    Van, L.D.: Design of efficient VLSI architectures: multiplier, 2-D digital filter and adaptive digital filter, Ph.D. dissertation, Department of the Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. (2001)Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  1. 1.Motilal Nehru National Institute of TechnologyAllahabadIndia

Personalised recommendations

Cite paper

Buy options