Advertisement

An Efficient High-Speed CORDIC Algorithm Using Parallel-Prefix Adders (PPA)

  • Vutukuri VenkateshEmail author
  • Balaji Yeswanth
  • Repala Akhil
  • Ravi Kumar Jatoth
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 587)

Abstract

Delay and Area ceases the actual potential of the modern gadgets. Although, human has sophisticated devices around him yet yearns to save time and space. So, this paper centers on the highly efficient CORDIC algorithm, known for its low-cost implementation in DSP algorithms. In an effort, to improve the algorithm further in terms of area and speed, comparative analysis has been done by replacing Ripple carry adder with Parallel-Prefix adders, namely, Brent-Kung adder, Han-Carlson adder and Kogge-Stone Adder. The algorithm was designed in VHDL using XILINX ISE 14.7 design suite and implemented in XILINX Spartan 6e FPGA. Obviously, Parallel-Prefix adders have shown improved performance.

Keywords

CORDIC algorithm Ripple carry adder Carry look ahead adder Kogge-Stone adder Brent-Kung adder Han-Carlson adder 

References

  1. 1.
    Anas, M.M., Padiyar, S., Boban, A.S.: Implementation of CORDIC algorithm and design of high speed CORDIC algorithm. In: International Conference on Energy, Communication, Data Analytics and Soft Computing (ICECDS-2017)Google Scholar
  2. 2.
    Rani, G., Kumar, S.: Delay analysis of parallel prefix adders. Int. J. Sci. Res. (IJSR)Google Scholar
  3. 3.
    Weinberger, Smith, J.: A logic for high-speed addition. Natl. Bur. Stand., No. Circ. 591, 3–12, 195Google Scholar
  4. 4.
    Basha, M.M., Ramanaiah, K.V., Reddy, P.R., Reddy, B.L.: An efficient model for design of 64-bit high speed parallel prefix VLSI adder. Int. J. Mod. Eng. Res. (IJMER) 3(5) (2013)Google Scholar
  5. 5.
    Kogge, P., Stone, H.: A parallel algorithm for the efficient solutions of a general class of recurrence relations. IEEE Trans. Comput. C 22(8) (1973)MathSciNetCrossRefGoogle Scholar
  6. 6.
    Pullarao, B., Kumar, J.P.: Design of high speed based on parallel prefix adders using in FPGA. Int. J. Eng. Sci. & Res. Technol. (IJESRT) (2013)Google Scholar
  7. 7.
    Han-Carlson: Fast area-efficient vlsi adders, IEEE (1987)Google Scholar
  8. 8.
    Vishal, R., Naik, S.K.: Design of a carry tree adder. International Journal of Pure and Applied Research in Engineering and Technology (IJPRET) 2(9), 413–424 (2014)Google Scholar
  9. 9.
    Lakshmi, B., Dhar, A.S.: CORDIC architectures: a surveyGoogle Scholar
  10. 10.
    Hoe, D.H.K., Martinez, C., Vundavalli, S.J.: Design and characterization of parallel prefix adders using FPGAsGoogle Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  • Vutukuri Venkatesh
    • 1
    Email author
  • Balaji Yeswanth
    • 1
  • Repala Akhil
    • 1
  • Ravi Kumar Jatoth
    • 2
  1. 1.Department of ECENational Institute of Technology, Andhra PradeshTadepalligudemIndia
  2. 2.Department of ECENational Institute of Technology, WarangalWarangalIndia

Personalised recommendations