A Hardware Minimized Gated Clock Multiple Output Low Power Linear Feedback Shift Register

  • Digvijay Singh Mehta
  • Varun Mishra
  • Yogesh Kumar Verma
  • Santosh Kumar GuptaEmail author
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 587)


As there is rapid increase in daily used battery-powered electronics equipment, and as these battery-powered equipments are able to work for a limited amount of time before requiring to recharge, there is ever increasing demand for long battery life (as run time on a full charge) that can be achieved by either increasing the battery capacity or reducing power consumption by the devices. In this paper, a switch minimized parallel LFSR with clock gating technique is proposed, and further optimization of circuit is performed by reducing number of gates (transistor) used by the circuit. Dynamic power consumption is reduced by minimizing the switching activity factor of the circuit, for which we utilize clock gating technique. Proposed circuit power consumption is compared with previous LFSR. The proposed circuit is implemented and simulated in cadence at 180 nm channel length, which verifies further reduction in power as compared to previous technique.


PRNG LFSR Low power Switching activity Hardware minimization 


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Copyright information

© Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  • Digvijay Singh Mehta
    • 1
  • Varun Mishra
    • 1
  • Yogesh Kumar Verma
    • 1
  • Santosh Kumar Gupta
    • 1
    Email author
  1. 1.Motilal Nehru National Institute of TechnologyAllahabadIndia

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