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Evaluation of Multiplier-Less DCT Transform Using In-Exact Computing

  • Uppugunduru Anil KumarEmail author
  • Nishant Jain
  • Sumit K. Chatterjee
  • Syed Ershad Ahmed
Conference paper
  • 57 Downloads
Part of the Communications in Computer and Information Science book series (CCIS, volume 1241)

Abstract

Discrete Cosine Transform (DCT) is an ubiquitous operation that tends to consume more power when implemented on hardware. In-exact computing, an emerging paradigm, aids to reduce the energy consumption in these error resilient image and video processing application. In this paper, we propose a new in-exact adder architecture which when implemented in DCT reduces the computational complexity that too without comprimising the peak signal-to-noise ratio (PSNR). Exhaustive PSNR and synthesis analysis prove that the proposed design performs better than existing adder architectures. The proposed design is implemented in 180 nm CMOS process technology node and results show that die area and power consumed are reduced upto 10% and 8% respectively.

Keywords

Discrete cosine transform In-exact computing In-exact adder 

Notes

Acknowledgment

This work is supported by BITS Pilani under Research Initiation Grant (RIG) pro-gram. The authors wish to thank and acknowledge the support received from BITS Pilani.

References

  1. 1.
    Vladimir, B., Patrick, C.Y., Rao, K.R.: Discrete cosine and sine transforms: general properties, fast algorithms and integer approximations. Elsevier (2010)Google Scholar
  2. 2.
    Bouguezel, S., Ahmad, M.O., Swamy, M.N.S.: Low-complexity 8\(\times \) 8 transform for image compression. Electron. Lett. 44(21), 1249–1250 (2008)CrossRefGoogle Scholar
  3. 3.
    Bouguezel, S., Ahmad, M.O., Swamy, M.N.S.: A low-complexity parametric transform for image compression. In 2011 IEEE International Symposium of Circuits and Systems (ISCAS), pp. 2145–2148. IEEE (2011)Google Scholar
  4. 4.
    Cintra, R.J., Bayer, F.M.: A dct approximation for image compression. IEEE Signal Process. Lett. 18(10), 579–582 (2011)CrossRefGoogle Scholar
  5. 5.
    Potluri, U.S., Madanayake, A., Cintra, R.J., Bayer, F.M., Kulasekera, S., Edirisuriya, A.: Improved 8-point approximate dct for image and video compression requiring only 14 additions. IEEE Trans. Circ. Syst. I Regul. Papers 61(6), 1727–1740 (2014)CrossRefGoogle Scholar
  6. 6.
    Arai, Y., Agui, T., Nakajima, M.: A fast dct-sq scheme for images. IEICE Trans. (1976–1990) 71(11), 1095–1097 (1988)Google Scholar
  7. 7.
    Liang, J., Tran, T.D.: Fast multiplierless approximations of the dct with the lifting scheme. IEEE Trans. Signal Process. 49(12), 3032–3044 (2001)CrossRefGoogle Scholar
  8. 8.
    Shin, D., Gupta, S.K.: Approximate logic synthesis for error tolerant applications. In: 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), pp. 957–960. IEEE (2010)Google Scholar
  9. 9.
    Gupta, V., Mohapatra, D., Raghunathan, A., Roy, K.: Low-power digital signal processing using approximate adders. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 32(1), 124–137 (2012)CrossRefGoogle Scholar
  10. 10.
    Liang, J., Han, J., Lombardi, F.: New metrics for the reliability of approximate and probabilistic adders. IEEE Trans. Comput. 62(9), 1760–1771 (2012)MathSciNetCrossRefGoogle Scholar
  11. 11.
    Jiang, H., Han, J., Lombardi, F.: A comparative review and evaluation of approximate adders. In: Proceedings of the 25th Edition on Great Lakes Symposium on VLSI, pp. 343–348 (2015)Google Scholar
  12. 12.
    Yang, Z., Jain, A., Liang, J., Han, J., Lombardi, F.: Approximate xor/xnor-based adders for inexact computing. In 2013 13th IEEE International Conference on Nanotechnology (IEEE-NANO 2013), pp. 690–693. IEEE (2013)Google Scholar
  13. 13.
    Almurib, H.A.F., Kumar, T.N., Lombardi, F.: Inexact designs for approximate low power addition by cell replacement. In 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 660–665. IEEE (2016)Google Scholar
  14. 14.
    Behrooz, P.: Computer Arithmetic, vol. 20. Oxford University Press, Cambridge (2010)Google Scholar
  15. 15.
    Mahdiani, H.R., Ahmadi, A., Fakhraie, S.M., Lucas, C.: Bio-inspired imprecise computational blocks for efficient vlsi implementation of soft-computing applications. IEEE Trans. Circ. Syst. I Regul. Papers 57(4), 850–862 (2009)MathSciNetCrossRefGoogle Scholar
  16. 16.
    Najafi, A., Weißbrich, W., Payá Vayá, G., Garcia-Ortiz, A.: A fair comparison of adders in stochastic regime. In: 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), pp. 1–6. IEEE (2017)Google Scholar
  17. 17.
    Zhu, N., Goh, W.L., Zhang, W., Yeo, K.S., Kong, Z.H.: Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 18(8), 1225–1229 (2010)CrossRefGoogle Scholar
  18. 18.
    Almurib, H.A.F., Kumar, T.N., Lombardi, F.: Approximate dct image compression using inexact computing. IEEE Trans. Comput. 67(2), 149–159 (2017)MathSciNetCrossRefGoogle Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  1. 1.BITS Pilani Hyderabad CampusHyderabadIndia

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