Evaluation of Multiplier-Less DCT Transform Using In-Exact Computing
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Discrete Cosine Transform (DCT) is an ubiquitous operation that tends to consume more power when implemented on hardware. In-exact computing, an emerging paradigm, aids to reduce the energy consumption in these error resilient image and video processing application. In this paper, we propose a new in-exact adder architecture which when implemented in DCT reduces the computational complexity that too without comprimising the peak signal-to-noise ratio (PSNR). Exhaustive PSNR and synthesis analysis prove that the proposed design performs better than existing adder architectures. The proposed design is implemented in 180 nm CMOS process technology node and results show that die area and power consumed are reduced upto 10% and 8% respectively.
KeywordsDiscrete cosine transform In-exact computing In-exact adder
This work is supported by BITS Pilani under Research Initiation Grant (RIG) pro-gram. The authors wish to thank and acknowledge the support received from BITS Pilani.
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