A Novel Approach for Design 7:3 and 5:3 Compressors
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The partial product reduction represents the major bottlenecks for low-power high-performance multiplier design. Conventionally, 3:2 compressor is used to reduce the partial products for binary multiplication. With the increase of input bit length, the complexity of aforesaid task becomes enormous. Use of multi-input compressor is an elegant way of reducing the complexity of partial product reduction especially for higher order multiplication. Two multi-input compressors, namely 5:3 and 7:3 compressors, are widely used for partial product reduction for binary multiplication. However, the performance of multi-input compressors decides the overall performance of the multiplier. This paper presents a new approach to design high-performance low-power 7:3 and 5:3 compressors for efficient multiplication. The proposed circuit has been designed using CMOS 0.18 µm TSMC technology process parameters. The performances of designed circuit are examined with T-Spice Tanner EDA V.13 at 25 °C temperature simulator. The designed circuit based on the proposed strategy outperforms other competitive designs.
KeywordsMulti-input compressor Parallel multiplier Partial product reduction Power dissipation Redundant carry generator
This work is supported by the Third Phase of Technical Education Quality Improvement Program (TEQIP-III) under the “TEQIP Collaborative Research Scheme”, National Project Implementation Unit (NPIU), a unit of Ministry of Human Resource Development (MHRD), Government of India, for implementation of World Bank assisted projects in technical education.
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