A Novel Approach for Design 7:3 and 5:3 Compressors

  • Ajay Kumar KushwahaEmail author
  • Vikas Kumar
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 1154)


The partial product reduction represents the major bottlenecks for low-power high-performance multiplier design. Conventionally, 3:2 compressor is used to reduce the partial products for binary multiplication. With the increase of input bit length, the complexity of aforesaid task becomes enormous. Use of multi-input compressor is an elegant way of reducing the complexity of partial product reduction especially for higher order multiplication. Two multi-input compressors, namely 5:3 and 7:3 compressors, are widely used for partial product reduction for binary multiplication. However, the performance of multi-input compressors decides the overall performance of the multiplier. This paper presents a new approach to design high-performance low-power 7:3 and 5:3 compressors for efficient multiplication. The proposed circuit has been designed using CMOS 0.18 µm TSMC technology process parameters. The performances of designed circuit are examined with T-Spice Tanner EDA V.13 at 25 °C temperature simulator. The designed circuit based on the proposed strategy outperforms other competitive designs.


Multi-input compressor Parallel multiplier Partial product reduction Power dissipation Redundant carry generator 



This work is supported by the Third Phase of Technical Education Quality Improvement Program (TEQIP-III) under the “TEQIP Collaborative Research Scheme”, National Project Implementation Unit (NPIU), a unit of Ministry of Human Resource Development (MHRD), Government of India, for implementation of World Bank assisted projects in technical education.


  1. 1.
    Saha, A., Pal, D., Chandra, M.: Low-power 6-GHz wave-pipelined 8b × 8b multiplier. IET Circuits Devices Syst. 7(3), 124–140 (2013). Scholar
  2. 2.
    Nirlakalla, R., Rao, T.S., Prasad, T.J.: Performance evaluation of high speed compressors for high speed multipliers. Serb. J. Electr. Eng. 8(3), 293–306 (2011).
  3. 3.
    Marimuthu, C.N., Thangaraj, P.: Transmission gate based high performance low power multiplier. J. Appl. Sci. 10(23), 3051–3059 (2010). Scholar
  4. 4.
    Baran, D., Aktan, M., Oklobdzija, V.G.: Energy efficient implementation of parallel CMOS multipliers with improved compressors. In: IEEE International Symposium on Low-Power Electronics and Design, pp. 147–152 (2010).
  5. 5.
    Dandapat, A., Ghosal, S., Sarkar, P., Mukhopadhyay, D.: A 1.2-ns 16 × 16-bit binary multiplier using high speed compressors. Int. J. Electr. Electron. Eng. 4(3) (2010)Google Scholar
  6. 6.
    Radhakrishnan, D., Preethy, A.P.: Low power CMOS pass logic 4-2 compressor for high speed multiplication. In: Proceedings of IEEE Midwest Symposium on Circuits and Systems, 3.3.31296–1298 (2000).
  7. 7.
    Najafi, A.A., Najafi, A., Mirzakuchaki, S.: Low-power and high-performance 5:2 compressors. In: The 22nd Iranian Conference on Electrical Engineering (ICEE), pp. 33–37 (2014).
  8. 8.
    Kushwaha, A.K., Paul, S.K.: Inductorless realization of Chua’s oscillator using DVCCTA. Analog Integr. Circ. Sig. Process. 88, 137–150 (2016).
  9. 9.
    Ramakrishnan, M., Bansal, D., Balamurugan, S., Mallick, P.S.: Design of 8-4 and 9-4 compressors for high speed multiplication. Am. J. Appl. Sci. 10(8), 893–900 (2013).
  10. 10.
    Menon, R., Radhakrishnan, D.: High performance 5:2 compressor architecture. IEEE Proc. Circ. Devices Syst. 153(5), 447–452 (2006). Scholar
  11. 11.
    Mishra, N., Sharma, T.K., Sharma, V., Vimal, V.: Secure framework for data security in cloud computing, soft computing: theories and applications. Adv. Intell. Syst. Comput. 61–71 (2018).

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© Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  1. 1.Government Engineering College RaipurRaipurIndia
  2. 2.Barat Sanchar Nigam LimitedPatnaIndia

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