Advertisement

Synthesis of Pseudorandom Number Generator by Combining Mentor Graphics HDL Designer and Xilinx Vivado FPGA Flow

  • Geethu Remadevi SomanathanEmail author
  • Ramesh Bhakthavathchalu
  • M. Krishnakumar
Conference paper
  • 35 Downloads
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 656)

Abstract

Pseudorandom number generators are used in cryptographic as well as VLSI testing applications. Linear Feedback Shift Registers (LFSR) are circuits that can be used as pseudorandom number generators. This paper proposes a modified reseeding method for LFSR and also presents a design flow for the implementation. The work is done by combining Mentor Graphics HDL Designer FPGA flow and Xilinx Vivado. Different bit lengths of LFSR are generated using Mentor Graphics HDL Designer and synthesized using both Mentor Graphics Precision RTL synthesizer and Xilinx Vivado. The implementation targets Virtex-7 FPGA.

Keywords

Pseudorandom number generator Linear feedback shift register Reseeding LFSR 

References

  1. 1.
    Youhua Shi ZZ (2003) Multiple test set generation method for LFSR-based BIST. In: Proceedings of the ASP-DAC Asia and South Pacific design automation conference, pp 863–868.  https://doi.org/10.1109/ASPDAC.2003.1195138
  2. 2.
    Dhingra S Comparison of LFSR and CA for BISTGoogle Scholar
  3. 3.
    Devika KN, Bhakthavatchalu R (2017) Design of reconfigurable LFSR for VLSI IC testing in ASIC and FPGA. In: International conference on communication and signal processing, 6–8 Apr 2017. India Design, pp. 928–932Google Scholar
  4. 4.
    Bushnell M, Agrawal V (2000) Essentials of electronic testing for digital, memory and mixed-signal VLSI circuitsGoogle Scholar
  5. 5.
    Wang L-T, Wu C-W, Wen X VLSI test principles and architecturesGoogle Scholar
  6. 6.
    Mukherjee N, Rajski J, Mrugalski G, Pogiel A, Tyszer J (2011) Ring generator : an ultimate linear feedback shift register. Computer (Long Beach Calif) 64–71.  https://doi.org/10.1109/MC.2010.334
  7. 7.
    Divyanjali TA (2015) A dissection of pseudorandom number generators. In: 2nd international conference on signal processing and integrated networks, SPIN 2015, pp 318–323.  https://doi.org/10.1109/SPIN.2015.7095369
  8. 8.
    Stpie R, Walczak J (2013) Comparative analysis of pseudo random signals of the LFSR and DLFSR generatorsGoogle Scholar
  9. 9.
    Datta D, Datta B, Dutta HS (2017) Design and implementation of multibit LFSR on FPGA to generate pseudorandom sequence number. In: Proceedings of 2nd international conference on 2017 devices for integrated circuit, DevIC 2017, pp 346–349.  https://doi.org/10.1109/DEVIC.2017.8073966
  10. 10.
    Prabha LS, Geethu RS (2018) Architecture of parallel CRC encoder using state space transformations. In: 2018 9th international conference on computing, communication and networking technologies, ICCCNT 2018. IEEE, pp 1–7.  https://doi.org/10.1109/ICCCNT.2018.8493862
  11. 11.
    Tehranipoor M (2012) Introduction to hardware security and trust. Springer, New York, NY.  https://doi.org/10.1007/978-1-4419-8080-9
  12. 12.
    Gergely AM, Crainicu B (2017) A succinct survey on (Pseudo)-random number generators from a cryptographic perspective. In: 2017 5th international symposium on digital forensic and security, ISDFS 2017, pp 1–6.  https://doi.org/10.1109/ISDFS.2017.7916504
  13. 13.
    Gayoso CA, González C, Arnone L, Rabini M, Moreira JC (2013) Pseudorandom number generator based on the residue number system and its FPGA implementation. In: Proceedings of the argentine school micro-nanoelectronics, technology and applications, EAMTA 2013Google Scholar
  14. 14.
    Garcia-Bosque M, Perez-Resa A, Sanchez-Azqueta C, Aldea C, Celma S (2019) Chaos-based bitwise dynamical pseudorandom number generator on FPGA. IEEE Trans Instrum Meas 68:291–293.  https://doi.org/10.1109/TIM.2018.2877859CrossRefGoogle Scholar
  15. 15.
    Dilip PS, Somanathan GR, Bhakthavatchalu R (2019) Reseeding LFSR for test pattern generation. In: Proceedings of the 2019 IEEE international conference on communication and signal processing, ICCSP 2019, pp 921–925.  https://doi.org/10.1109/ICCSP.2019.8698025
  16. 16.
    Wang W-L, Lee K-J (2002) An efficient deterministic test pattern generator for Scan-Based BIST EnvironmentGoogle Scholar
  17. 17.
    Hoare RR, Tung SC (2003) Combining mentor graphics’ HDL designer FPGA flow with a reconfigurable system on a programmable chip, educational opportunity or insanity? In Proceedings of the 2003 IEEE international conference on microelectronic systems education, tomorrow’s microsystems designers, MSE 2003, pp 128–130.  https://doi.org/10.1109/MSE.2003.1205286
  18. 18.
    Xilinx Inc (2015) Vivado design suite user guide-design analysis and closure techniquesGoogle Scholar
  19. 19.
    Xilinx Inc (2015) Vivado design suite user guide-using the Vivado IDEGoogle Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringAmrita Vishwa VidyapeethamAmritapuriIndia
  2. 2.KSEB LtdThiruvananthapuramIndia

Personalised recommendations