Advertisement

Solder Joints in PCB Assembly and Semiconductor Packaging

  • John H. Lau
  • Ning-Cheng Lee
Chapter
  • 82 Downloads

Abstract

Assembly and reliability of lead-free solder joints are very important topics in electronic manufacturing. There are many books [1–69] and papers [70–315] written on them. In this book, the assembly of lead-free solder joints such as prevailing lead-free materials, soldering processes, advanced specialty flux design, and characterization of lead-free solder joints will be discussed, respectively in Chaps.  2 5. The reliability of lead-free solder joints such as reliability testing and data analyses, design for reliability, and failure analyses of lead-free solder joints will be discussed, respectively in Chaps.  6 8. The special features of this book are the materials covered are not only for electronic manufacturing services (EMS) on the second-level interconnects, but also for packaging assembly on the first-level interconnects and for the semiconductor back-end on the 2.5D and 3D IC integration interconnects as shown in Fig. 1.1. The solder joints in various plated-through hole (PTH) and surface mount technology (SMT) printed circuit board (PCB) assemblies, and semiconductor packages will be discussed in this chapter.

References

  1. 1.
    Tummala R, Swaminathan M (2008) System on package: miniaturization of the entire system. McGraw-Hill, New York, NYGoogle Scholar
  2. 2.
    Shina S (2008) Green electronics: design and manufacturing. McGraw-Hill, New YorkzbMATHGoogle Scholar
  3. 3.
    Lee T, Bieler T, Kim C, Ma H (2015) Fundamentals of lead-free solder interconnect technology. Springer, New YorkCrossRefGoogle Scholar
  4. 4.
    Liu Y (2012) Power electronic packaging. Springer, New YorkCrossRefGoogle Scholar
  5. 5.
    Liu S, Liu Y (2011) Modeling and simulation for microelectronic packaging assembly. Wiley, New YorkCrossRefGoogle Scholar
  6. 6.
    Pang J (2018) Lead-free solder: mechanics and reliability. Springer, New YorkGoogle Scholar
  7. 7.
    Perkins A, Sitaraman S (2009) Solder joint reliability prediction for multiple environments. Springer, New YorkCrossRefGoogle Scholar
  8. 8.
    Tamin M, Shaffiar N (2014) Solder joint reliability assessment. Springer, New YorkCrossRefGoogle Scholar
  9. 9.
    Tu KN (2007) Solder joint technology. Springer, New YorkGoogle Scholar
  10. 10.
    Madenci E, Guven I, Kilic B (2003) Fatigue life prediction of solder joints in electronic packages with ANSYS. Springer, New YorkCrossRefGoogle Scholar
  11. 11.
    Tummala R (2001) Fundamentals of microsystems packaging. McGraw-Hill, New York, NYGoogle Scholar
  12. 12.
    Remsburg R (2001) Thermal design of electronic equipment. CRC Press, New York, NYGoogle Scholar
  13. 13.
    Prasad RP (1997) Surface mount technology: principles and practice, 2nd edn. Chapman & Hall, New YorkCrossRefGoogle Scholar
  14. 14.
    Harper CA (1997) Electronic packaging and interconnection handbook, 2nd edn. McGraw Hill, New YorkGoogle Scholar
  15. 15.
    Woodgate RW (1996) The handbook of machine soldering: SMT and TH, 3rd edn. John Wiley & Sons, Inc., New YorkGoogle Scholar
  16. 16.
    Hwang JS (1996) Modern solder technology for competitive electronics manufacturing. McGraw Hill, New YorkGoogle Scholar
  17. 17.
    Harman G (1997) Wire bonding in microelectronics: materials, processes, reliability, and yield. McGraw Hill, New YorkGoogle Scholar
  18. 18.
    Fjelstad J (1997) An engineer’s guide to flexible circuit technology. Electrochemical Publications, Ayr, Great BritainGoogle Scholar
  19. 19.
    Elshabini-Riad A, Barlow FD III (1997) Thin film technology handbook. McGraw-Hill, New York, NYGoogle Scholar
  20. 20.
    Konsowski SG, Helland AR (1997) Electronic packaging of high speed circuitry. McGraw-Hill, New York, NYGoogle Scholar
  21. 21.
    DiGiacomo G (1996) Reliability of electronic packages and semiconductor devices. McGraw-Hill, New York, NYGoogle Scholar
  22. 22.
    Qu S, Liu Y (2016) Wafer-level chip-scale packaging, Springer, New YorkGoogle Scholar
  23. 23.
    Liu J (1999) Conductive adhesives for electronics packaging. Electrochemical Publications, Isle of Man, British IslesGoogle Scholar
  24. 24.
    Lee NC (2002) Reflow soldering processes and troubleshooting: SMT. BGA, CSP, and Flip Chip Technologies. NEWNES, New YorkGoogle Scholar
  25. 25.
    Lau JH (2019) Heterogeneous integrations. Springer, New YorkCrossRefGoogle Scholar
  26. 26.
    Lau JH (2018) Fan-out wafer-level packaging. Springer, New YorkCrossRefGoogle Scholar
  27. 27.
    Lau JH (2016) 3D IC integration and packaging. McGraw-Hill, New YorkGoogle Scholar
  28. 28.
    Lau JH (2013) Through silicon via (TSV) for 3D integration. McGraw-Hill, New YorkGoogle Scholar
  29. 29.
    Lau JH (2011) Reliability of RoHS-compliant 2D and 3D IC interconnects. McGraw-Hill, New YorkGoogle Scholar
  30. 30.
    Lau JH, Lee CK, Premachandran CS, Yu A (2010) Advanced MEMS packaging. McGraw-Hill, New YorkGoogle Scholar
  31. 31.
    Lau JH, Wong CP, Lee NC, Lee SW (2003) Electronics manufacturing with lead-free, halogen-free and conductive-adhesive materials. McGraw-Hill, New YorkGoogle Scholar
  32. 32.
    Lau JH, Ricky Lee SW (2001) Microvias for low cost, high density interconnects. McGraw-Hill, New YorkGoogle Scholar
  33. 33.
    Lau JH (2000) Low cost flip chip technologies. McGraw-Hill, New YorkGoogle Scholar
  34. 34.
    Lau JH, Ricky Lee SW (1999) Chip scale package. McGraw-Hill, New YorkGoogle Scholar
  35. 35.
    Lau JH, Wong CP, Prince J, Nakayama W (1998) Electronic packaging: design, materials, process, and reliability. McGraw-Hill, New YorkGoogle Scholar
  36. 36.
    Lau JH, Pao Y-H (1997) Solder joint reliability of BGA, CSP, flip chip and fine pitch SMT assemblies. McGraw-Hill, New YorkGoogle Scholar
  37. 37.
    Lau JH (ed) (1996) Flip chip technologies. New York, McGraw-HillGoogle Scholar
  38. 38.
    Lau JH (ed) (1995) Ball grid array technology. McGraw-Hill, New York, NYGoogle Scholar
  39. 39.
    Lau JH (ed) (1994) Chip on board: technologies for multichip modules. Van Nostrand Reinhold, New YorkGoogle Scholar
  40. 40.
    Lau JH (ed) (1994) Handbook of fine pitch surface mount technology. Van Nostrand Reinhold, New YorkGoogle Scholar
  41. 41.
    Frear D, Morgan H, Burchett S, Lau JH (eds) (1994) The mechanics of solder alloy interconnects. Van Nostrand Reinhold, New YorkGoogle Scholar
  42. 42.
    Lau JH (ed) (1993) Thermal stress and strain in microelectronics packaging. Van Nostrand Reinhold, New YorkGoogle Scholar
  43. 43.
    Lau JH (ed) (1992) Handbook of tape automated bonding. Van Nostrand Reinhold, New York, NYGoogle Scholar
  44. 44.
    Lau JH (ed) (1991) Solder joint reliability: theory and applications. Van Nostrand Reinhold, New York, NYGoogle Scholar
  45. 45.
    Ross RJ, Boit C, Staab D (eds) (1999) Microelectronic failure analysis: desk reference, 4th edn. ASM International, Materials Park, OHGoogle Scholar
  46. 46.
    Blackwell GR (ed) (1999) The electronic packaging handbook. CRC Press, Boca Raton, FLGoogle Scholar
  47. 47.
    Brown W (ed) (1999) Advanced electronic packaging: with emphasis on multichip modules. IEEE Press, Piscataway, NJGoogle Scholar
  48. 48.
    Azar K (ed) (1997) Thermal measurements in electronic cooling. CRC Press, New York, NYGoogle Scholar
  49. 49.
    Lee YC, Chen WT (eds) (1998) Manufacturing challenges in electronic packaging. London, Chapman & HallGoogle Scholar
  50. 50.
    Puttlitz K, Totta P (eds) (2001) Area array interconnection handbook. Kluwer Academic Publishers, BostonGoogle Scholar
  51. 51.
    Shangguan D (ed) (2005) Lead-free solder joint interconnect reliability. ASM International, Materials Park, OHGoogle Scholar
  52. 52.
    Bath J (ed) (2007) Lead-free soldering. Springer, New YorkGoogle Scholar
  53. 53.
    Puttlitz K, Stalter K (eds) (2005) Handbook of lead-free solder technology for microelectronic assemblies. Marcel Dekker, New YorkGoogle Scholar
  54. 54.
    Tummala RR, Rymaszewski EJ (eds) (1989) Microelectronics packaging handbook. Van Nostrand Reinhold, New York, NYGoogle Scholar
  55. 55.
    Tummala RE, Rymasewski EJ, Klopfenstein AG (eds) (1997) Microelectronics packaging handbook: semiconductor packaging (Part II), 2nd edn. New York, Chapman & HallGoogle Scholar
  56. 56.
    Tummala RE, Rymasewski EJ, Klopfenstein AG (eds) (1997) Microelectronics packaging handbook: subsystem packaging (Part III), 2nd edn. New York, Chapman & HallGoogle Scholar
  57. 57.
    Lu D, Wong CP (eds) (2008) Materials for advanced packaging. Springer, New York, NYGoogle Scholar
  58. 58.
    Suhir E, Lee YC, Wong CP (eds) (2007) Micro- and opto-electronic materials and structures: physics, mechanics, design, reliability, packaging. Springer, New York, NYGoogle Scholar
  59. 59.
    Tong H, Lai Y, Wong CP (eds) (2013) Advanced flip chip packaging. Springer, New YorkGoogle Scholar
  60. 60.
    Garrou P, Bower C, Ramm P (eds) (2008) Handbook of 3D integration. Wiley, WeinheimGoogle Scholar
  61. 61.
    Xie Y, Cong J, Sapatnekar S (eds) (2010) Three-dimensional integrated circuit design. Springer, New YorkGoogle Scholar
  62. 62.
    Wu B, Kumar A, Ramaswami S (eds) (2011) 3D IC stacking technology. McGraw-Hill, New YorkGoogle Scholar
  63. 63.
    Subramanian K (ed) (2012) Lead-free solders: materials reliability for electronics. John Wiley & Sons, New YorkGoogle Scholar
  64. 64.
    Sharif A (ed) (2019) Harsh environment electronics, interconnect materials and performance assessment. Wiley, New YorkGoogle Scholar
  65. 65.
    Mahidhara RK, Frear DR, Sastry SML, Murty KL, Liaw P, Winterbottom WL (1997) Design and reliability of solders and solder interconnections. TMS Minerals Metals Materials, Warrendale, PAGoogle Scholar
  66. 66.
    Mickelson AR, Basavanhally NR, Lee YC (eds) (1997) Optoelectronic packaging. John Wiley & Sons, New YorkGoogle Scholar
  67. 67.
    Wagner LC (ed) (1999) Failure analysis of integrated circuits: tools and techniques. Kluwer Academic Publishers, Boston/Dordrecht/LondonGoogle Scholar
  68. 68.
    Harper CA (ed) (2000) Electronic packaging and interconnection handbook, 3rd edn. McGraw-Hill, Inc., New York, NYGoogle Scholar
  69. 69.
    McCluskey FP, Grzybowski R, Podlesak T (eds) (1997) High temperature electronics. CRC Press, New York, NYGoogle Scholar
  70. 70.
    Davis E, Harding W, Schwartz R, Corning J (1964) Solid logic technology: versatile, high performance microelectronics. IBM J Res Develop 8:102–114CrossRefGoogle Scholar
  71. 71.
    Totta P, Sopher R (1969) SLT device metallurgy and its monolithic extension. IBM J Res Develop 5:226–238CrossRefGoogle Scholar
  72. 72.
    Love D, Moresco L, Chou W, Horine D, Wong C, and Beilin S (1994) Wire interconnect structures for connecting an integrated circuit to a substrate. US Patent 5,334,804Google Scholar
  73. 73.
    Tung F (2003) Pillar connections for semiconductor chips and method of manufacture. US Patent 6,578,754Google Scholar
  74. 74.
    Tung F (2003) Pillar connections for semiconductor chips and method of manufacture. US Patent 6,592,019Google Scholar
  75. 75.
    Tung F (2004) Pillar connections for semiconductor chips and method of manufacture. US Patent 6,681,982Google Scholar
  76. 76.
    Amkor Data Sheet (2019) Flip chip ball grid array (fcBGA)Google Scholar
  77. 77.
    Huang S, Zhan C, Huang Y, Lin Y, Fan C, Chung S, Kao K, Chang J, Wu M, Yang T, Lau JH, Chen T (2012) Effects of UBM structure/material on the reliability performance of 3D chip stacking with 30μm-pitch solder micro bump interconnections. IEEE/ECTC Proceedings, pp 1287–1292Google Scholar
  78. 78.
    Li L, Su P, Xue J, Brillhart M, Lau JH, Tzeng P, Lee C, Zhan C, Dai M, Chien H, Wu S (2012) Addressing bandwidth challenges in next generation high performance network systems with 3D IC integration. IEEE ECTC Proceedings, San Diego, CA, pp 1040–1046Google Scholar
  79. 79.
    Ji M, Li M, Cline J, Seeker D, Cai K, Lau JH, Tzeng P, Zhan C, Lee C (2013) 3D Si interposer design and electrical performance study. Proceedings of DesignCon, Santa Clara, CA, January 2013, pp 1–23Google Scholar
  80. 80.
    Brunnbauer M, Fürgut E, Beer G, Meyer T, Hedler H, Belonio J, et al. (2006) An embedded device technology based on a molded reconfigured wafer. IEEE/ECTC Proceedings, May 2006, pp 547–551Google Scholar
  81. 81.
    Jin Y, Teysseyre J, Baraton X, Yoon S, Lin Y, Marimuthu P (2012) Development and characterization of next generation eWLB (embedded Wafer Level BGA) packaging. IEEE/ECTC Proceedings, May 2012, pp 1388–1393Google Scholar
  82. 82.
    Sharma G, Lakhera N, Benson M, Mawer A (2019) Advanced fan out wafer level package development for small for factor and high-performance microcontroller applications. Proceedings of the International Wafer-Level Packaging Conference, October 2019, pp 1–6Google Scholar
  83. 83.
    Hwang T, Oh D, Song E, Kim K, Kim J, Lee S (2018) Study of advanced fan-out packages for mobile applications. IEEE/ECTC Proceedings, May 2018, pp 343–348Google Scholar
  84. 84.
    Lee M, Yoo M, Cho J, Lee S, Kim J, Lee C, Kang D, Zwenger C, Lanzone R (2009) Study of interconnection process for fine pitch flip chip. IEEE/ECTC Proceedings, May 2009, pp 720–723Google Scholar
  85. 85.
    Tseng C-F, Liu C-S, Wu C-H, Yu D (2016) InFO (wafer level integrated fan-out) technology. IEEE/ECTC Proceedings, May 2016, pp 1–6Google Scholar
  86. 86.
    Shimizu N, Kaneda W, Arisaka H, Koizumi N, Sunohara S, Rokugawa A, Koyama T (2013) Development of organic multi chip package for high performance application. IMAPS International Symposium on Microelectronics, Orlando, FL, 30 September–3 October 2013, pp 414–419CrossRefGoogle Scholar
  87. 87.
    Oi K, Otake S, Shimizu N, Watanabe S, Kunimoto Y, Kurihara T, Koyama T, Tanaka M, Aryasomayajula L, Kutlu Z (2014) Development of new 2.5D package with novel integrated organic interposer substrate with ultra-fine wiring and high density bumps. IEEE/ECTC Proceedings, May 2014, pp 348–353Google Scholar
  88. 88.
    Banijamali B, Chiu C, Hsieh C, Lin T, Hu C, Hou S, et al. (2013) Reliability evaluation of a CoWoS-enabled 3D IC package. IEEE/ECTC Proceedings, May 2013, pp 35–40Google Scholar
  89. 89.
    McCann S, Lee H, Refai-Ahmed G, Lee T, Ramalingam S (2018) Warpage and reliability challenges for stacked silicon interconnect technology in large packages. IEEE/ECTC Proceedings, May 2018, pp 2339–2344Google Scholar
  90. 90.
    Chiu C, Qian Z, Manusharow M (2014) Bridge interconnect with air gap in package assembly. US Patent 8,872,349Google Scholar
  91. 91.
    Mahajan R, Sankman R, Patel N, Kim D, Aygun K, Qian Z, et al. (2016) Embedded multi-die interconnect bridge (EMIB)—a high-density, high-bandwidth packaging interconnect. IEEE/ECTC Proceedings, May 2016, pp 557–565Google Scholar
  92. 92.
    Hou S, Chen W, Hu C, Chiu C, Ting K, Lin T, et al. (2017) Wafer-level integration of an advanced logic-memory system through the second-generation CoWoS technology. IEEE Transactions on Electron Devices, October 2017, pp 4071–4077CrossRefGoogle Scholar
  93. 93.
    Zhang R, Lee R, Xiao D, Chen H (2011) LED packaging using silicon substrate with cavities for phosphor printing and copper-filled TSVs for 3D interconnection. IEEE/ECTC Proceedings, May 2011, pp 1616–1621Google Scholar
  94. 94.
    Zhang R, Lee R (2012) Moldless encapsulation for LED wafer level packaging using integrated DRIE trenches. J Microelectron Reliab 52:922–932CrossRefGoogle Scholar
  95. 95.
    Zoschke K, Manier C-A, Wilke M, Jürgensen N, Oppermann H, Ruffieux D, Dekker J, Heikkinen H, Piazza S, Allegato G, Lang K-D (2013) Hermetic wafer level packaging of MEMS components using through silicon via and wafer to wafer bonding technologies. IEEE/ECTC Proceedings, Las Vegas, NV, May 2013, pp 1500–1507Google Scholar
  96. 96.
    Coudrain P, Henry D, Berthelot A, Charbonnier J, Verrun S, Franiatte R, Bouzaida N, Cibrario G, Calmony F, O’Connory I, Lacrevazz T, Fourneaudz L, Flechetz B, Chevrier N, Farcy A, Le-Briz O (2013) 3D integration of CMOS image sensor with coprocessor using TSV last and micro-bumps technologies. IEEE/ECTC Proceedings, Las Vegas, NV, May 2013, pp 674–682Google Scholar
  97. 97.
    Li L, Chia P, Ton P, Nagar M, Patil S, Xue J, et al. (2016) 3D SiP with organic interposer of ASIC and memory integration. IEEE/ECTC Proceedings, May 2016, pp 1445–1450Google Scholar
  98. 98.
    Yoon SW, Tang P, Emigh R, Lin Y, Marimuthu PC, Pendse R (2013) Fanout flipchip eWLB (embedded wafer level ball grid array) technology as 2.5D packaging solutions. IEEE/ECTC Proceedings, May 2013, pp 1855–1860Google Scholar
  99. 99.
    Lin Y, Lai W, Kao C, Lou J, Yang P, Wang C, et al. (2016) Wafer warpage experiments and simulation for fan-out chip-on-substrate. IEEE/ECTC Proceedings, May 2016, pp 13–18Google Scholar
  100. 100.
    Suk K, Lee S, Kim J, Lee S, Kim H, Lee S, et al. (2018) Low cost Si-less RDL interposer package for high performance computing applications. IEEE/ECTC Proceedings, May 2018, pp 64–69Google Scholar
  101. 101.
    Yu D (2018). Advanced system integration technology trends. SEMICON Taiwan, September 2018Google Scholar
  102. 102.
    Tunga K, Ross J, Sikka K, Parikh B (2019) Fatigue life prediction model development for decoupling capacitors. IEEE/ECTC Proceedings, May 2019, pp 1121–1129Google Scholar
  103. 103.
    Ahari A, Hsiao A, Baty G, Su P, Lee T (2019) Microstructure signature evolution in solder joints, solder bumps, and micro-bumps interconnection in a large 2.5D FCBGA package during thermo-mechanical cycling. IEEE/ECTC Proceedings, May 2019, pp 1099–1105Google Scholar
  104. 104.
    Wu J, Suhling JC, Lall P (2019) Microstructural evolution in SAC+X solders subjected to aging. IEEE/ECTC Proceedings, May 2019, pp 1087–1098Google Scholar
  105. 105.
    Madanipour H, Kim Y, Kim C, Shahane N, Mishra D, Noguchi T, Yoshino M, Nguyen L (2019) Effect of intermetallic compound growth on electromigration failure mechanism in low-profile solder joints. IEEE/ECTC Proceedings, May 2019, pp 1316–1323Google Scholar
  106. 106.
    Hassan K, Alam MS, Suhling JC, Lall P (2019) The Poisson’s ratio of lead free solder—the often forgotten but important material property. IEEE/ECTC Proceedings, May 2019, pp 1958–1969Google Scholar
  107. 107.
    Su S, Hoque M, Chowdhury M, Hamasha S, Suhling JC, Evans JL, Lall P (2019) Mechanical properties and microstructural fatigue damage evolution in cyclically loaded lead-free solder joints. IEEE/ECTC Proceedings, May 2019, pp 792–799Google Scholar
  108. 108.
    Waidhas B, Proschwitz J, Pietryga C, Wagner T, Keser B (2019) Study of the board level reliability performance of a large 0.3 mm pitch wafer level package. IEEE/ECTC Proceedings, May 2019, pp 1159–1164Google Scholar
  109. 109.
    Huang M, Kuang JM, Sun HY (2019) Electromigration-induced β-Sn grain rotation in lead-free flip chip solder bumps. IEEE/ECTC Proceedings, May 2019, pp 2036–2041Google Scholar
  110. 110.
    Liu L, Luo D, Lu T, Xiao H (2019) Research on applied reliability of BGA solder balls in extreme marine environment. IEEE/ECTC Proceedings, May 2019, pp 2054–2060Google Scholar
  111. 111.
    Park J, Park J, Paik K (2019) Low temperature transient liquid phase (TLP) bonding using eutectic Sn-In solder anisotropic conductive films (ACFs) for flexible ultrasound transducer. IEEE/ECTC Proceedings, May 2019, pp 2213–2218Google Scholar
  112. 112.
    Loh W, Hsu C, Kulterman R, Fu H (2019) Impact of low temperature solder on electronic package dynamic warpage behavior and requirement. IEEE/ECTC Proceedings, May 2019, pp 318–324Google Scholar
  113. 113.
    Huang PS, Yu CK, Chiang WS, Lin MZ, Fang YH, Lin MJ, Liu NW, Lin B, Hsu I (2019) Reliability investigation of extremely large ratio fan-out wafer-level package with low ball density for ultra-short-range radar. IEEE/ECTC Proceedings, May 2019, pp 493–497Google Scholar
  114. 114.
    Xu J, McCann S, Wang H, Wang J, Pham V, Cain SR, Ahmed G, Park SB (2019) An assessment of electromigration in 2.5D packaging. IEEE/ECTC Proceedings, May 2019, pp 2150–2155Google Scholar
  115. 115.
    Kim Y, Hah J, Zelaia P, Lee S, Christie L, Houston P, Melkote S, Moon K, Wong C (2019) Microstructures of Pb-free solder joints by reflow and thermo-compression bonding (TCB) processes. IEEE/ECTC Proceedings, May 2019, pp 2349–2358Google Scholar
  116. 116.
    Ahmed O, Jalilvand G, Fernandez H, Su P, Lee T, Jiang T (2019) Long-term reliability of solder joints in 3D ICs under near-application conditions. IEEE/ECTC Proceedings, May 2019, pp 1106–1112Google Scholar
  117. 117.
    Fu X, Zhou B, Yao R, En Y, Chen S (2019) Effect of grain orientation and microstructure evolution on electromigration in flip-chip solder joint. IEEE/ECTC Proceedings, May 2019, pp 1324–1327Google Scholar
  118. 118.
    Miki S, Taneda H, Kobayashi N, Oi K, Nagai K, Koyama T (2019) Development of 2.3D high density organic package using low temperature bonding process with Sn-Bi Solder. IEEE/ECTC Proceedings, May 2019, pp 1599–1604Google Scholar
  119. 119.
    Shen Y, Zhou S, Li J, Tu KN, Nishikawa H (2019) Microstructure and property changes in Cu/Sn-58Bi/Cu solder joints during thermomigration. IEEE/ECTC Proceedings, May 2019, pp 2003–2008Google Scholar
  120. 120.
    Zhang S, Huang M, Wu Y, Yang M, Lin T, He P, Paik K (2019) A study on the oxygen plasma treatment on the peel adhesion strength and solder wettability of SnBi58 based anisotropic conductive films. IEEE/ECTC Proceedings, May 2019, p 2028Google Scholar
  121. 121.
    Kencana S, Kuo Y, Yen Y, Schellkes E (2019) Improving the solder wettability via atmospheric plasma technology. IEEE/ECTC Proceedings, May 2019, pp 2067–2071Google Scholar
  122. 122.
    Zhanga W, Jia H, Lia M, Zhao W (2019) Ultrasonic-accelerated intermetallic joint formation with composite solder for high-temperature power device packaging. IEEE/ECTC Proceedings, May 2019, pp 183–190Google Scholar
  123. 123.
    Xie D, Hai J, Wu Z, Economou M (2019) Solder joint reliability of double-side mounted DDR modules for consumer and automotive applications. IEEE/ECTC Proceedings, May 2019, pp 486–492Google Scholar
  124. 124.
    Shimada S, Okada K, Kudo T, Ueta C, Suzuki Y (2019) High reliability solder resist with strong adhesion and high resolution for high density packaging. IEEE/ECTC Proceedings, May 2019, pp 1015–1021Google Scholar
  125. 125.
    Kim B, Ryu D, Jeon H, Hazellah M, Chim W, Khim J (2019) Pb-free, high thermal and electrical performance driven die attach material development for power packages. IEEE/ECTC Proceedings, May 2019, pp 1457–1462Google Scholar
  126. 126.
    Vitello D, Albertinetti A, Rovitto M (2019) Die thickness optimization for preventing electro-thermal fails induced by solder voids in power devices. IEEE/ECTC Proceedings, May 2019, pp 2091–2096Google Scholar
  127. 127.
    Gagnon P, Fortin C, Weiss T (2019) Package-on-package micro-BGA microstructure interaction with bond and assembly parameters. IEEE/ECTC Proceedings, May 2019, pp 306–313Google Scholar
  128. 128.
    Gupte O, Teoh K, Tummala R, Murtagian G (2019) Innovative socketable and surface-mountable BGA interconnections. IEEE/ECTC Proceedings, May 2019, pp 1028–1034Google Scholar
  129. 129.
    Serebreni M, Hernandez N, Sharon G, Blattau N, Hillman C, Symonds K (2019) Improved correlation between accelerated board level reliability (BLR) testing and customer BLR results using a hybrid closed-form/finite element methodology. IEEE/ECTC Proceedings, May 2019, pp 2013–2111Google Scholar
  130. 130.
    Dias R, Kelly M, Balaraman D, Shoji H, Shiraiwa T, Oh K, Park J (2019) Challenges and approaches to developing automotive grade 1/0 FCBGA package capability. IEEE/ECTC Proceedings, May 2019, pp 163–167Google Scholar
  131. 131.
    Chong S, Siang S (2019) Comprehensive study of copper nano-paste for Cu–Cu bonding. EEE/ECTC Proceedings, May 2019, pp 191–196Google Scholar
  132. 132.
    Meier K, Winkler M, Bock K, Leslie D, Dasgupta A (2019) Fatigue behaviour of lead-free solder joints under combined thermal and vibration loads. IEEE/ECTC Proceedings, May 2019, pp 498–504Google Scholar
  133. 133.
    Gao G, Mirkarimi L, Workman T, Fountain G, Theil J, Guevara G, Liu P, Lee B, Mrozek P, Huynh M, Rudolph C, Werner T, Hanisch A (2019) Low temperature Cu interconnect with chip to wafer hybrid bonding. IEEE/ECTC Proceedings, May 2019, pp 628–635Google Scholar
  134. 134.
    Lau JH (2019) Recent advances and trends in fan-out wafer/panel-level packaging. J Electron Packag 141:1–27CrossRefGoogle Scholar
  135. 135.
    Lau JH (2019) Overview and outlook for heterogeneous integrations. Chip Scale Rev 23:34–40Google Scholar
  136. 136.
    Lau JH (2019) Recent advances and trends in heterogeneous integrations. J Microelectron Electron Packag 16(2):45–77CrossRefGoogle Scholar
  137. 137.
    Lau JH (2019) Redistribution-layers for heterogeneous integrations. Chip Scale Rev 23:20–25Google Scholar
  138. 138.
    Lau JH, Lee NC et al (2018) Reliability of fan-out wafer-level heterogeneous integration. J Microelectron Electron Packag 15(4):148–162CrossRefGoogle Scholar
  139. 139.
    Lau JH, Lee NC et al (2018) Fan-out wafer-level packaging for heterogeneous integration. IEEE Trans CPMT 8(9):1544–1560Google Scholar
  140. 140.
    Ko CT, Yang H, Lau JH, Lee NC et al (2018) Design, materials, process, and fabrication of fan-out panel-level heterogeneous integration. J Microelectron Electron Packag 15(4):141–147CrossRefGoogle Scholar
  141. 141.
    Lau JH, Lee NC et al (2018) Design, materials, process, and fabrication of fan-out wafer-level packaging. IEEE Trans CPMT 8(6):991–1002Google Scholar
  142. 142.
    Ko CT, Lau JH, Lee NC et al (2018) Chip-first fan-out panel level packaging for heterogeneous integration. IEEE Trans CPMT 8(9):1561–1572Google Scholar
  143. 143.
    Lau JH, Lee NC et al (2018) Warpage measurements and characterizations of FOWLP with large chips and multiple RDLs. IEEE Trans CPMT 8(10):1729–1737Google Scholar
  144. 144.
    Lau JH (2018) 8 ways to make RDLs for FOW/PLP. Chip Scale Rev 22:11–19Google Scholar
  145. 145.
    Lau JH (2018) 3D IC heterogeneous integration by FOWLP. Chip Scale Rev 22:16–21Google Scholar
  146. 146.
    Lau JH, Lee NC et al (2017) Fan-out wafer-level packaging (FOWLP) of large chip with multiple redistribution layers (RDLs). J Microelectron Electron Packag 14(4):123–131CrossRefGoogle Scholar
  147. 147.
    Lau JH, Lee NC et al (2017) Warpage and thermal characterization of fan-out wafer-level packaging. IEEE Trans CPMT 7(10):1729–1738Google Scholar
  148. 148.
    Lau JH (2017) Recent advances and trends in advanced packaging. Chip Scale Rev 21:46–54Google Scholar
  149. 149.
    Lau JH (2016) Recent advances and new trends in flip chip technology. J Electron Packag 138(3):1–23CrossRefGoogle Scholar
  150. 150.
    Lau JH (2016) TSV-less interposers. Chip Scale Rev 20:28–35Google Scholar
  151. 151.
    Lau JH, Fan N, Li M (2016) Design, material, process, and equipment of embedded fan-out wafer/panel-level packaging. Chip Scale Rev 20:38–44Google Scholar
  152. 152.
    Lau JH (2015) Patent issues of fan-out wafer/panel-level packaging. Chip Scale Rev 19:42–46Google Scholar
  153. 153.
    Lau JH, Li M, Fan N, Tse R (2015) Thermocompression bonding for flip-chip technology. Chip Scale Rev 19:30–36Google Scholar
  154. 154.
    Lau JH, Zhang Q, Li M, Yeung K et al (2015) Stencil printing of underfill for flip chips on organic-panel and Si-wafer substrates. IEEE Trans CPMT 5(7):1027–1035Google Scholar
  155. 155.
    Lau JH (2015) Semiconductor and packaging for internet of things. Chip Scale Rev 19:25–30Google Scholar
  156. 156.
    Lau JH (2014) Overview and outlook of 3D IC packaging, 3D IC integration, and 3D Si integration. J Electron Packag 136(4):1–15CrossRefGoogle Scholar
  157. 157.
    Lau JH, Lee C, Zhan C et al (2014) Low-cost through-silicon hole interposers for 3D IC integration. IEEE Trans CPMT 4(9):1407–1419Google Scholar
  158. 158.
    Lau JH, Tzeng P, Lee C, Zhan C, Li M et al (2014) Redistribution layers (RDLs) for 2.5D/3D IC integration. J Microelectron Packag 11(1):16–24CrossRefGoogle Scholar
  159. 159.
    Lau JH (2014) The future of interposer for semiconductor IC packaging. Chip Scale Rev 18(1):32–36Google Scholar
  160. 160.
    Hsieh MC, Wu ST, Wu CJ, Lau JH (2014) Energy release rate estimation for through silicon vias in 3-D integration. IEEE Trans CPMT 4(1):57–65Google Scholar
  161. 161.
    Lau JH (2013) Supply chains for high-volume manufacturing of 3D IC integration. Chip Scale Rev 17(1):33–39Google Scholar
  162. 162.
    Khan N, Li H, Tan S, Ho S, Kripesh V, Pinjala D, Lau JH, Chuan T (2013) 3-D Packaging with through-silicon via (TSV) for electrical and fluidic interconnections. IEEE Trans CPMT 3(2):221–228Google Scholar
  163. 163.
    Lee CC, Wu C, Kao K, Fang C, Zhan C, Lau JH, Chen TH (2013) Impact of high density TSVs on the assembly of 3D-ICs packaging. Microelectron Eng 107:101–106CrossRefGoogle Scholar
  164. 164.
    Lau JH, Tang GY (2012) Effects of TSVs (through-silicon vias) on thermal performances of 3D IC integration system-in-package (SiP). J Microelectron Reliab 52(11):2660–2669CrossRefGoogle Scholar
  165. 165.
    Lau JH (2012) Recent advances and new trends in nanotechnology and 3D integration for semiconductor industry. ECS Trans 44(1):805–825CrossRefGoogle Scholar
  166. 166.
    Chien HC, Lau JH, Chao Y, Tain R, Dai M, Wu ST, Lo W, Kao MJ (2012) Thermal performance of 3D IC integration with through-silicon via (TSV). J Microelectron Packag 9:97–103CrossRefGoogle Scholar
  167. 167.
    Chen JC, Lau JH, Tzeng PJ et al (2012) Effects of slurry in Cu chemical mechanical polishing (CMP) of TSVs for 3-D IC integration. IEEE Trans CPMT 2(6):956–963Google Scholar
  168. 168.
    Lee CK, Chang TC, Lau JH, Huang Y et al (2012) Wafer bumping, assembly, and reliability of fine-pitch lead-free micro solder joints for 3-D IC integration. IEEE Trans CPMT 2(8):1229–1238Google Scholar
  169. 169.
    Chai TC, Zhang X, Li H, Sekhar V, Kalandar O, Khan N, Lau JH, Murthy R, Tan Y, Cheng C, Liew S, Chi D (2012) Impact of packaging design on reliability of large die Cu/low-κ (BD) interconnect. IEEE Trans CPMT 2(5):807–816Google Scholar
  170. 170.
    Zhang X, Rajoo R, Selvanayagam CS, Kumar A, Rao V, Khan N, Kripesh V, Lau JH, Kwong D, Sundaram V, Tummala RR (2012) Application of piezoresistive stress sensor in wafer bumping and drop impact test of embedded ultrathin device. IEEE Trans CPMT 2(16):935–943Google Scholar
  171. 171.
    Wu C, Chen S, Tzeng P, Lau JH, Hsu Y, Chen J, Hsin Y, Chen C, Shen S, Lin C, Ku T, Kao M (2012) Oxide liner, barrier and seed layers, and Cu-plating of blind through silicon vias (TSVs) on 300 mm wafers for 3D IC integration. J Microelectron Packag 9(1):31–36CrossRefGoogle Scholar
  172. 172.
    Lau JH, Zhang MS, Lee SWR (2011) Embedded 3D hybrid IC integration system-in-package (SiP) for opto-electronic interconnects in organic substrates. J Electron Packag 133:1–7CrossRefGoogle Scholar
  173. 173.
    Chai TC, Zhang X, Lau JH, Selvanayagam CS et al (2011) Development of large die fine-pitch Cu/low-k FCBGA package with through silicon via (TSV) interposer. IEEE Trans CPMT 1(5):660–672Google Scholar
  174. 174.
    Lau JH (2011) TSV interposers: the most cost-effective integrator for 3D IC integration. Chip Scale Rev 15(5):23–27Google Scholar
  175. 175.
    Sharma G, Rao V, Kumar A, Lim Y, Houe K, Lim S, Sekhar V, Rajoo R, Kripesh V, Lau JH (2011) Design and development of multi-die laterally placed and vertically stacked embedded micro-wafer-level packages. IEEE Trans CPMT 1(5):52–59Google Scholar
  176. 176.
    Kumar A, Zhang X, Zhang Q, Jong M, Huang G, Lee V, Kripesh V, Lee C, Lau JH, Kwong D, Sundaram V, Tummula RR, Meyer-Berg G (2011) Residual stress analysis in thin device wafer using piezoresistive stress sensor. IEEE Trans CPMT 1(6):841–851Google Scholar
  177. 177.
    Yu A, Lau JH, Ho S, Kumar A et al (2011) Fabrication of high aspect ratio TSV and assembly with fine-pitch low-cost solder microbump for Si interposer technology with high-density interconnects. IEEE Trans CPMT 1(9):1336–1344Google Scholar
  178. 178.
    Ong YY, Ho S, Sekhar V, Ong X, Ong J, Zhang X, Kripesh V, Yoon S, Lau JH, Lim Y et al (2011) Underfill selection, characterization, and reliability study for fine-pitch, large die Cu/low-k flip chip package. IEEE Trans CPMT 1(3):279–290Google Scholar
  179. 179.
    Zhang X, Lau JH, Premachandran CS et al (2011) Development of a Cu/Low-k stack die fine pitch ball grid array (FBGA) package for system in package applications. IEEE Trans CPMT 1(3):299–309Google Scholar
  180. 180.
    Lau JH (2011) Overview and outlook of TSV and 3D integrations. J Microelectron Int 28(2):8–22CrossRefGoogle Scholar
  181. 181.
    Lau JH, Zhan C-J, Tzeng P-J, Lee C-K et al (2011) Feasibility study of a 3D IC integration system-in-packaging (SiP) from a 300 mm multi-project wafer (MPW). J Microelectron Electron Packag 8(4):171–178CrossRefGoogle Scholar
  182. 182.
    Sheu S, Lin Z, Hung J, Lau JH, Chen P, Wu S, Su K, Lin C, Lai S, Ku T, Lo W, Kao M (2011) An electrical testing method for blind through silicon vias (TSVs) for 3D IC integration. J Microelectron Electron Packag 8(4):140–145CrossRefGoogle Scholar
  183. 183.
    Lau JH (2010) Critical issues of 3D IC integrations. J Microelectron Electron Packag:35–43Google Scholar
  184. 184.
    Lau JH, Chan YS, Lee RSW (2010) 3D IC integration with TSV interposers for high-performance applications. Chip Scale Rev 14(5):26–29Google Scholar
  185. 185.
    Lau JH (2010) Design and process of 3D MEMS packaging. J Microelectron Electron Packag:10–15Google Scholar
  186. 186.
    Lau JH, Lee R, Yuen M, Chan P (2010) 3D LED and IC wafer level packaging. J Microelectron Int 27(2):98–105CrossRefGoogle Scholar
  187. 187.
    Lau JH (2010) State-of-the-art and trends in 3D integration. Chip Scale Rev 14(2):22–28Google Scholar
  188. 188.
    Ong Y, Ho S, Kripesh V, Sekhar V, Jong M, Long S, Lee V, Leong W, Rao V, Ong J, Ong X, Zhang X, Yoon S, Lau JH, Lim Y, Yeo D, Chan K, Zhang Y, Tan J, Sohn D (2010) Design, assembly and reliability of large die and fine-pitch Cu/low-k flip chip package. J Microelectron Reliab 50:986–994CrossRefGoogle Scholar
  189. 189.
    Tang GY, Tan S, Khan N, Pinjala D, Lau JH, Yu A, Kripesh V, Toh K (2010) Integrated liquid cooling systems for 3-D stacked TSV modules. IEEE Trans CPMT 33(1):184–195Google Scholar
  190. 190.
    Rao V, Zhang X, Ho S, Rajoo R, Premachandran CS, Kripesh V, Yoon S, Lau JH (2010) Design and development of fine pitch copper/low-K wafer level package. IEEE Trans Adv Packag 33(2):377–388CrossRefGoogle Scholar
  191. 191.
    Khan N, Rao V, Lim S, We H, Lee V, Zhang X, Liao E, Nagarajan R, Chai TC, Kripesh V, Lau JH (2010) Development of 3-D silicon module with TSV for system in packaging. IEEE Trans CPMT 33(1):3–9Google Scholar
  192. 192.
    Lim S, Rao V, Hnin W, Ching W, Kripesh V, Lee C, Lau JH, Milla J, Fenner A (2010) Process development and reliability of microbumps. IEEE Trans CPMT 33(4):747–753Google Scholar
  193. 193.
    Lim Y, Xiao X, Vempati R, Nandar S, Aditya K, Gaurav S, Lim T, Kripesh V, Shi J, Lau JH, Liu S (2010) Higg quality and low loss millimeter wave passives demonstrated to 77-GHz for SiP technologies using embedded wafer-level packaging platform (EMWLP). IEEE Trans Adv Packag 33:1061–1071CrossRefGoogle Scholar
  194. 194.
    Lee C, Yu A, Yan L, Wang H, Han J, Zhang Q, Lau JH (2009) Characterization of intermediate In/Ag layers of low temperature fluxless solder based wafer bonding for MEMS packaging. J Sens Actuator A Phys 154:85–91CrossRefGoogle Scholar
  195. 195.
    Yu D-Q, Lee C, Yan LL, Thew ML, Lau JH (2009) Characterization and reliability study of low temperature hermetic wafer level bonding using In/Sn interlayer and Cu/Ni/Au metallization. J Alloy Compd 485:444–450CrossRefGoogle Scholar
  196. 196.
    Yu DQ, Lee C, Yan LL, Choi WK, Yu A, Lau JH (2009) The role of Ni buffer layer on high yield low temperature hermetic wafer bonding using In/Sn/Cu metallization. Appl Phys Lett 94(3):1–3CrossRefGoogle Scholar
  197. 197.
    Made R, Gan C, Yan L, Yu A, Yoon S, Lau JH, Lee C (2009) Study of low temperature thermocompression bonding in Ag-In solder for packaging applications. J Electron Mater 38(2):365–371CrossRefGoogle Scholar
  198. 198.
    Yan LL, Lee CK, Yu DQ, Yu A, Choi W, Lau JH, Yoon S (2009) A hermetic seal using composite thin solder In/Sn as intermediate layer and its interdiffusion reaction with Cu. J Electron Mater 38(2):200–207CrossRefGoogle Scholar
  199. 199.
    Dauksher W, Lau JH (2009) A finite-element-based solder-joint fatigue-life prediction methodology for Sn–Ag–Cu ball-grid-array packages. IEEE Trans Dev Mater Reliab 9(2):231–236CrossRefGoogle Scholar
  200. 200.
    Yu DQ, Li Y, Lee C, Choi W, Thew S, Foo C, Lau JH (2009) Wafer-level hermetic bonding using Sn/In and Cu/Ti/Au metallization. IEEE Trans CPMT 32(4):926–934Google Scholar
  201. 201.
    Yu A, Khan N, Archit G, Pinjala D, Toh K, Kripesh V, Yoon S, Lau JH (2009) Fabrication of silicon carriers with TSV electrical interconnections and embedded thermal solutions for high power 3-D packages. IEEE Trans CPMT 32(3):566–571Google Scholar
  202. 202.
    Selvanayagam C, Lau JH, Zhang X, Seah S, Vaidyanathan K, Chai TC (2009) Nonlinear thermal stress/strain analyses of copper filled TSV (through silicon via) and their flip-chip microbumps. IEEE Trans Adv Packag 32(4):720–728CrossRefGoogle Scholar
  203. 203.
    Lau JH, Gleason J, Schroeder V, Henshall G, Dauksher W, Sullivan B (2008) Design, materials, and assembly process of high-density packages with a low-temperature lead-free solder (SnBiAg). Solder Surf Mount Technol 20(2):11–20CrossRefGoogle Scholar
  204. 204.
    Lau JH, Gleason J, Schroeder V, Henshall G, Dauksher W, Sullivan B (2008) Reliability test and failure analysis of high-density packages assembled with a low-temperature lead-free solder (SnBiAg). Solder Surf Mount Technol 20(2):21–29CrossRefGoogle Scholar
  205. 205.
    Lau JH, Castello T, Shangguan D, Dauksher W, Smetana J, Horsley R, Love D, Menis I, Sullivan B (2007) Failure analysis of lead-free solder joints of an 1657CCGA (ceramic column grid array) package. J Microelectron Electron Packag 4(3):189–213CrossRefGoogle Scholar
  206. 206.
    Lau JH (2006) Reliability of lead-free solder joints. J Electron Packag 128:297–301CrossRefGoogle Scholar
  207. 207.
    Lau JH (2005) Reliability of an 1657CCGA (ceramic column grid array) package with 96.5Sn3.9Ag0.6Cu lead-free solder paste on pcbs (printed circuit boards). J Electron Packag 127:96–105CrossRefGoogle Scholar
  208. 208.
    Lau JH, Dauksher W, Smetana J, Horsley R, Shangguan D, Castello T, Menis I, Love D, Sullivan B (2004) Design for lead-free solder joint reliability of high-density packages. J Sold Surf Mount Technol 16(1):12–26CrossRefGoogle Scholar
  209. 209.
    Lau JH, Hoo N, Horsley R, Smetana J, Shangguan D, Dauksher W, Love D, Menis I, Sullivan B (2004) Reliability testing and data analysis of lead-free solder joints for high-density packages. J Sold Surf Mount Technol 16(2):46–68CrossRefGoogle Scholar
  210. 210.
    Lau JH, Smetana J, Horsley R, Snowdon K, Shangguan D, Gleason J, Memis I, Love D, Dauksher W, Sullivan B (2004) Design, materials, and process for lead-free assembly of high-density packages. J Sold Surf Mount Technol 16(1):53–62CrossRefGoogle Scholar
  211. 211.
    Lau JH, Shangguan D, Castello T, Horsley R, Smetana J, Dauksher W, Love D, Menis I, Sullivan B (2004) Failure analysis of lead-free solder joints for high-density packages. J Sold Surf Mount Technol 16(2):69–76CrossRefGoogle Scholar
  212. 212.
    Lau JH et al (2003) 3D Nonlinear stress analysis of tin whisker initiation on lead-free components. J Electron Packag 125:621–624CrossRefGoogle Scholar
  213. 213.
    Lau JH et al (2002) Creep Analysis and thermal-fatigue life prediction of the lead-free solder sealing ring of a photonic switch. J Electron Packag 124:403–410CrossRefGoogle Scholar
  214. 214.
    Lau JH, Chang C (2002) Characteristics and reliability of fast-flow, snap-cure, and reworkable underfills for solder bumped flip chip on low-cost substrates. IEEE Trans Electron Packag Manuf 25(3):231–230CrossRefGoogle Scholar
  215. 215.
    Lau JH (2002) Critical issues of wafer level chip scale package (WLCSP) with emphasis on cost analysis and solder joint reliability. IEEE Trans Electron Packag Manuf 25(1):42–50CrossRefGoogle Scholar
  216. 216.
    Lau JH, Lee R (2002) Effects of build-up printed circuit board thickness on the solder joint reliability of a wafer level chip scale package (WLCSP). IEEE Trans Component Packag Technol 25(1):3–14CrossRefGoogle Scholar
  217. 217.
    Lau JH, Pan S, Chang C (2002) A new thermal-fatigue life prediction model for wafer level chip scale package (WLCSP) solder joints. J Electron Packag 124:212–220CrossRefGoogle Scholar
  218. 218.
    Lau JH, Lee R (2002) Modeling and analysis of 96.5Sn-3.5Ag lead-free solder joints of wafer level chip scale package (WLCSP) on build-up microvia printed circuit board. IEEE Trans Electron Packag Manuf 25(1):51–58CrossRefGoogle Scholar
  219. 219.
    Lau JH, Lee R, Pan S, Chang C (2002) Nonlinear time-dependent analysis of micro via-in-pad substrates for solder bumped flip chip applications. J Electron Packag 124:205–211CrossRefGoogle Scholar
  220. 220.
    Lau JH, Chang C, Lee R (2001) Solder joint crack propagation analysis of wafer-level chip scale package on printed circuit board assemblies. IEEE Trans Component Packag Technol 24(2):285–292CrossRefGoogle Scholar
  221. 221.
    Lau JH, Lee R (2001) Computational analysis on the effects of double-layer build-up printed circuit board on the wafer level chip scale package (WLCSP) assembly with Pb-free solder joints. Int J Microelectron Electron Packag IMAPS Trans 24(2):89–104Google Scholar
  222. 222.
    Lau JH, Lee R, Chang C (2000) Solder joint reliability of wafer level chip scale package (WLCSP): a time-temperature-dependent creep analysis. J Electron Packag 122(4):311–316CrossRefGoogle Scholar
  223. 223.
    Lau JH, Lee R (2000) Fracture mechanics analysis of low cost solder bumped flip chip assemblies with imperfect underfills. J Electron Packag 122(4):306–310CrossRefGoogle Scholar
  224. 224.
    Lau JH (2000) Cost analysis: solder bumped flip chip vs. wire bonding. IEEE Trans Electron Packag Manuf 23:4–11CrossRefGoogle Scholar
  225. 225.
    Lau JH, Chang C, Lee R (2000) Failure analysis of solder bumped flip chip on low-cost substrates. IEEE Trans Electron Packag Manuf 23(1):19–27CrossRefGoogle Scholar
  226. 226.
    Lau JH, Chang C (2000) Taguchi design of experiment for wafer bumping by stencil printing. IEEE Trans Electron Packag Manuf 21(3):219–225CrossRefGoogle Scholar
  227. 227.
    Lau JH, Lee R, Chang C (2000) Effects of underfill material properties on the reliability of solder bumped flip chip on board with imperfect underfill encapsulants. IEEE Trans CPMT:323–333Google Scholar
  228. 228.
    Lau JH, Chang C, Lee SWR, Chen TY, Cheng D, Tseng TJ, Lin D (2000) Design and manufacturing of micro via-in-pad substrates for solder bumped flip chip applications. J Electron Manuf 10(1):79–87CrossRefGoogle Scholar
  229. 229.
    Lau JH, Lee SW (2000) Effects of underfill delamination and chip size on the reliability of solder bumped flip chip on board. Int J Microelectron Electron Packag IMAPS Trans 23(1):33–39Google Scholar
  230. 230.
    Lau JH, Lee R (2000) Temperature-dependent popcorning analysis of plastic ball grid array package during solder reflow with fracture mechanics method. J Electron Packag 122:34–41CrossRefGoogle Scholar
  231. 231.
    Lau JH, Lee R, Chao H (1999) Assembly of large pbgas on printed circuit board with large PQFPs directly on the opposite side. J Electron Manuf 9(4):293–298CrossRefGoogle Scholar
  232. 232.
    Lau JH, Chang C, Chen C (1999) Characteristics and reliability of no-flow underfills for solder bumped flip chip assemblies. Int J Microelectron Electron Packag IMAPS Trans 22(4):370–381Google Scholar
  233. 233.
    Lau JH, Chang C (1999) Delamination analysis of plastic packages during solder reflow by strain-gage measurement and tomographic acoustic micro imaging methods. J Electron Manuf 8:165–172CrossRefGoogle Scholar
  234. 234.
    Lau JH, Chang C, Lee M, Cheng D, Tseng T (1999) Printed circuit board manufacturing and testing of RIMM. J Electron Manuf 9(3):215–222CrossRefGoogle Scholar
  235. 235.
    Lau JH, Chang C (1999) How to select underfill materials for solder bumped flip chips on low cost substrates? Int J Microelectron Electron Packag IMAPS Trans 22(1):20–28Google Scholar
  236. 236.
    Lau JH (1999) Design, manufacturing, and testing of a novel plastic ball grid array package. J Electron Manuf 9(4):283–291CrossRefGoogle Scholar
  237. 237.
    Lau JH, Chang C (1999) Characterization of underfill materials for functional solder bumped flip chips on board applications. IEEE Trans CPMT Part A 22(1):111–119Google Scholar
  238. 238.
    Lau JH, Chen T, Lee R (1999) Effect of heat spreader sizes on the thermal performance of large cavity-down plastic ball grid array packages. J Electron Packag 121(4):242–248CrossRefGoogle Scholar
  239. 239.
    Lau JH, Chang C (1999) TMA, DMA, DSC, and TGA of lead free solders. J Sold Surf Mount Technol 11(2):17–24CrossRefGoogle Scholar
  240. 240.
    Lau JH, Chang C, Ouyang C (1998) SMT compatible no-flow underfill for solder bumped flip chip on low-cost substrates. J Electron Manuf 8(3 & 4):151–164CrossRefGoogle Scholar
  241. 241.
    Lau JH (1998) Solder joint reliability of a low cost chip size package—NuBGA. J Microelectron Reliab 38:1519–1529CrossRefGoogle Scholar
  242. 242.
    Lau JH et al (1998) A low-cost solder-bumped chip scale package—NuCSP. J Inst Interconnect Technol 24(3):11–25Google Scholar
  243. 243.
    Lau JH, Chen KL (1997) Thermal and mechanical evaluations of a cost-effective plastic ball grid array package. J Electron Packag 119:208–212CrossRefGoogle Scholar
  244. 244.
    Lau JH, Lee R (1998) Solder joint reliability of cavity-down plastic ball grid array assemblies. J Sold Surf Mount Technol 10(1):26–31CrossRefGoogle Scholar
  245. 245.
    Lau JH (1997) Nonlinear analysis of full-matrix and perimeter plastic ball grid array solder joints. J Electron Packag:163–170Google Scholar
  246. 246.
    Lau JH, Chang C, Chen R (1997) Effects of underfill encapsulant on the mechanical and electrical performance of a functional flip chip device. J Electron Manuf 7(4):269–277CrossRefGoogle Scholar
  247. 247.
    Lau JH, Chen KL (1997) Thermal and mechanical evaluation of a cost-effective plastic ball grid array package. J Electron Packag 119:208–212CrossRefGoogle Scholar
  248. 248.
    Lau JH, Jung W, Pao Y (1997) Nonlinear analysis of full-matrix and perimeter plastic ball grid array solder joints. J Electron Packag 119:163–170CrossRefGoogle Scholar
  249. 249.
    Lau JH (1997) The roles of DNP (distance to neutral point) on solder joint reliability of area array assemblies. J Sold Surf Mount Technol 20:58–60CrossRefGoogle Scholar
  250. 250.
    Lau JH, Lee R (1997) Design for plastic ball grid array solder joint reliability. J Inst Interconnect Technol 23(2):11–13Google Scholar
  251. 251.
    Lau JH (1996) Solder joint reliability of flip chip and plastic ball grid array assemblies under thermal, mechanical, and vibration conditions. IEEE Trans CPMT Part B 19(4):728–735Google Scholar
  252. 252.
    Lau JH, Lee R (1996) Effect of chip dimension and substrate thickness on the solder joint reliability of plastic ball grid array package. J Inst Interconnect Technol 23:16–19Google Scholar
  253. 253.
    Lau JH, Schneider E, Baker T (1996) Shock and vibration of solder bumped flip chip on organic coated copper boards. J Electron Packag 118:101–104CrossRefGoogle Scholar
  254. 254.
    Lau JH, Gratalo K, Schneider E, Marcotte T, Baker T (1995) Solder joint reliability of large plastic ball grid array assemblies. J Inst Interconnect Technol 22:27–32Google Scholar
  255. 255.
    Lau JH, Kelley M (1995) Low cost solder bumped flip chip MCM-L demonstration. J Inst Interconnect Technol 21:159–164Google Scholar
  256. 256.
    Lau JH, Heydinger M, Glazer J, Uno D (1995) Design and procurement of eutectic solder-bumped flip chip test die and organic substrates. J Inst Interconnect Technol 21:20–24Google Scholar
  257. 257.
    Lau JH, Wun B (1995) Characterization and evaluation of the underfill encapsulants for flip chip assembly. J Inst Interconnect Technol 21:25–27Google Scholar
  258. 258.
    Lau JH, Golwalkar S, Erasmus S (1994) Advantages and disadvantages of thin small outline packages (TSOP) with copper gull-wing leads. J Electron Packag 116:234–237CrossRefGoogle Scholar
  259. 259.
    Lau JH (1994) Bending and twisting of solder interconnects with creep. J Electron Packag:154–157Google Scholar
  260. 260.
    Lau JH, Miremadi J, Gleason J, Haven R, Ottoboni S, Mimura S (1994) No clean mass reflow of large plastic ball grid array carriers. J Instit Interconnect Technol 20:15–22Google Scholar
  261. 261.
    Lau JH, Pao Y, Larner C, Twerefour S, Govila R, Gilbert D, Eeasmus S, Dolot S (1994) Reliability of 0.4mm pitch, 256-pin plastic quad flat pack no-clean and water-clean solder joints. J Sold Surf Mount Technol 16:42–50CrossRefGoogle Scholar
  262. 262.
    Lau JH (1993) Creep of solder interconnections under combined loads. IEEE Trans CPMT:794–798Google Scholar
  263. 263.
    Lau JH, Erasmus S (1993) Reliability of fine pitch plastic quad flat pack leads and solder joints under bending, twisting, and thermal conditions. J Electron Packag 115:322–328CrossRefGoogle Scholar
  264. 264.
    Lau JH, Marcotte T, Severine J, Lee A, Erasmus S, Baker T, Moldaschel J, Sporer M, Burward-Hoy G (1993) Solder joint reliability of surface mount connectors. J Electron Packag 115:180–188CrossRefGoogle Scholar
  265. 265.
    Lau JH, Golwalkar S, Boysan P, Surratt R, Rice D, Forhringer R, Erasmus S (1993) Solder joint reliability of a thin small outline package (TSOP). J Instit Interconnect Technol 20(1):12–19Google Scholar
  266. 266.
    Lau JH (1993) Creep of 96.5Sn3.5Ag solder interconnects. J Sold Surf Mount Technol 15:45–49CrossRefGoogle Scholar
  267. 267.
    Lee N-C (1996) Getting ready for lead free solders. European Surface Mount Conference, Brighton, UKGoogle Scholar
  268. 268.
    Lee N-C (1999) Lead-free soldering—where the world is going. Advancing Microelectronics magazine, September/October 1999Google Scholar
  269. 269.
    Lee N-C (2019) Achieving high reliability for lead-free solder joints—materials consideration. SMTA International Conference, Professional Development Course, Rosemont, IL, 22 September 2019Google Scholar
  270. 270.
    Sn995 Cobalt-Doped Pb-Free Soldering Alloy. Indium Corporation, Product Data Sheet, 98572Google Scholar
  271. 271.
    Lee N-C, Liu W (2016) Lead-free solder alloys and solder joints thereof with improved drop impact resistance. US Patent 9,260,768, 16 February 2016Google Scholar
  272. 272.
    WO 2007/081775 A2, Lead-free solder with low Cu dissolutionGoogle Scholar
  273. 273.
    Huang B, Hwang H-S, Lee N-C (2008) A compliant and creep resistant SAC-Al(Ni) alloy. APEX, Las Vegas, Nevada, 1–3 April 2008Google Scholar
  274. 274.
    Lee N-C (2000) Lead-free soldering and low alpha solders for wafer level interconnects. SMTA International, 2000—ChicagoGoogle Scholar
  275. 275.
    Lee N-C (2017) Short course “Choosing solders for the new era: low cost high reliability solder alloys. IMAPS, , Raleigh, North Carolina, 9–12 October 2017Google Scholar
  276. 276.
    Indium Corporation product data sheet on Sn995Google Scholar
  277. 277.
    Goudarzi V, Brown M, Liu W, Lee N-C, Lee JCB (2013) The second generation shock resistant and thermally reliable low Ag SAC solder doped with Mn. SMTA International, Fort Worth, TX, 13–17 October 2013Google Scholar
  278. 278.
    Geng J, Zhang H, Mutuku F, Lee N-C (2015) Novel lead-free solder alloys development for automotive applications. SMTA International, Rosemont, IL, 27 September–1 October 2015Google Scholar
  279. 279.
    Lee N-C, Reflow soldering processes and troubleshooting—SMT, BGA, CSP and flip chip technologies. Newnes, pp 269, 2001Google Scholar
  280. 280.
    Hance W, Lee N-C (1993) Voiding mechanisms in SMT. China Lake’s 17th Annual Electronics Manufacturing SeminarCrossRefGoogle Scholar
  281. 281.
    Herron D, Liu Y, Lee N-C (2011) Pad design and process for voiding control at QFN assembly. APEX, San Diego, CA, 28 February–1 March 2011Google Scholar
  282. 282.
    Liu Y, Manning W, Huang B, Lee N-C (2005) A model study of profiling for voiding control at lead-free reflow soldering. Nepcon Shanghai, China, 11 April 2005Google Scholar
  283. 283.
    Jo H, Nieman B, Lee N-C (2002) Voiding of lead-free soldering at microvia. In Proceedings of IMAPS, Denver, CO, September 2002Google Scholar
  284. 284.
    Dasgupta A, Lee N-C (2004) Effect of lead-free alloys on voiding at microvia. Apex, Anaheim, CA, February 2004Google Scholar
  285. 285.
    Hance WB, Lee N-C (1995) Voiding in BGA. In Proceedings of 1995 ISHM, Los Angeles, CA, p 535Google Scholar
  286. 286.
    Ohara W, Lee N-C (1993) Voiding mechanisms in SMT. China Lake’s 17th Annual Electronics Manufacturing SeminarGoogle Scholar
  287. 287.
    Lee N-C (2001) Reflow soldering processing and troubleshooting SMT, BGA, CSP, and Flip Chip Technologies. Newnes, p 288Google Scholar
  288. 288.
    Liu Y, Herron D, Keck J, Lee N-C (2012) Voiding behavior in mixed solder alloy system. SMTA International, Orlando, FL, 14–18 October 2012Google Scholar
  289. 289.
    Liu Y, Keck J, Page E, Lee N-C (2014) Voiding and drop test performance of lead-free low melting and medium melting mixed alloy BGA assembly. APEX, Las Vegas, NV, 25–27 March 2014Google Scholar
  290. 290.
    Jo H, Nieman BE, Lee N-C (2004) Effect of lead-free alloys on voiding at microvia. Apex, Anaheim, CA, 23–27 February 2004Google Scholar
  291. 291.
    Liu Y, Fiacco P, Lee N-C (2010) Testing and prevention of head-in-pillow. ECTC, Las Vegas, NV, June 1–4, 2010Google Scholar
  292. 292.
    Jaeger PA, Lee N-C (1992) A model study of low residue no-clean solder paste, Nepcon West, Anaheim, CAGoogle Scholar
  293. 293.
    Zhou F, Chen F, Lee N-C (2018) Fluxes effective in suppressing non-wet-open at BGA assembly. IMAPS, Pasadena, CA, 8–11 October 2018CrossRefGoogle Scholar
  294. 294.
    Lee N-C, Evans G (1985) Solder paste: meeting the SMT challenge. SITE Magazine, June 1987Google Scholar
  295. 295.
    Hance WB, Jaeger PA, Lee N-C (1991) Solder beading in SMT—cause and cure. SMIGoogle Scholar
  296. 296.
    Hwang J, Lee N-C (1985) A new development in solder paste with unique rheology for surface mounting. Proceedings of the International Symposium on Microelectronics, November 1985, pp 23–30.Google Scholar
  297. 297.
    Mao R, Chen F, Lee N-C (2019) Fluxes with decreased viscosity after reflow for flip chip and sip assembly. IMAPS, Boston, MA, 30 September–4 October 2019CrossRefGoogle Scholar
  298. 298.
    US Patent 10,010,981, Materials having increased mobility after heatingGoogle Scholar
  299. 299.
    Chen F, Lee N-C (1993) The risk of no-clean flux not fully dried under component terminations. SMTA China East, Shanghai, China, 20–23 April 2015Google Scholar
  300. 300.
    Lee N-C (2005) Critical parameters in voiding control at reflow soldering. Chip Scale Review, August–September 2005Google Scholar
  301. 301.
    Lee N-C (2002) Flux technology for lead-free alloys & its impact on cleaning. SMTA International, Chicago, IL, September 2002Google Scholar
  302. 302.
    Liu Y, Fiacco P, Lee N-C (2010) Testing and prevention of head-in-pillow. Surface Mount Technology Association (SMTA) China South Conference at NEPCON Shenzhen, August 2010Google Scholar
  303. 303.
    Xiao M, Jaeger PA, Lee N-C (1997) Probe testability of no-clean solder pastes, Nepcon WestGoogle Scholar
  304. 304.
    Hu M, Kresge L, Lee N-C (2011) Epoxy flux—a low cost high reliability approach for pop assembly. International Microelectronics Assembly and Packaging Society (IMAPS) Conference, Long Beach, CA, 9–13 October 2011Google Scholar
  305. 305.
    Yin W, Beckwith G, Hwang H-S, Kresge L, Lee N-C (2002) Epoxy flux—an answer for low cost no-clean flip chip assembly. Nepcon West/Fiberoptic Automation Expo, San Jose, CA, 3–6 December 2002Google Scholar
  306. 306.
    Yin W, Lee N-C (2003) A novel epoxy flux for lead-free soldering. International Brazing and Soldering Conference, San Diego, CA, 16–21 February 2003Google Scholar
  307. 307.
    Yin W, Beckwith G, Hwang H-S, Lee N-C (2002) Low cost no-flow underfilling being a reality for manufacturing. Nepcon West/Fiberoptic Automation Expo, San Jose, CA, 3–6 December 2002Google Scholar
  308. 308.
    Jaeger P, Lee N-C (1992) A model study of low residue no-clean solder paste, Nepcon West, Anaheim, CAGoogle Scholar
  309. 309.
    Lee N-C, Evans G (1987) Solder paste: meeting the smt challenge. SITE Magazine, June 1987Google Scholar
  310. 310.
    Hance WB, Jaeger PA, Lee N-C (1991) Solder beading in SMT—cause and cure. Proceedings of Surface Mount International, San Jose, California, August 1991, p 210Google Scholar
  311. 311.
    Keck J, Lee N-C (2017) Assessment of solder paste technology limitation at miniaturization for SIP and SMT Application. ICEPT, Harbin, China, 16–19 August 2017Google Scholar
  312. 312.
    Xiao M, Lawless KJ, Lee N-C (1993) Prospects of solder paste in ultra fine pitch era. SMI, San Jose, CA, 31 August–2 September 1993, pp 454–468Google Scholar
  313. 313.
    Lee N-C (2007) Future lead-free solder alloys and fluxes—Meeting challenges of miniaturization. International Microsystems, Packaging, Assembly and Circuits Technology (IMPACT) conference, Taipei, Taiwan, 1–3 October 2007Google Scholar
  314. 314.
    Lee N-C (2019) Short course on “Achieving high reliability of lead-free solder joints”. ECTC, Las Vegas, Nevada, USA, 28–31 May 2019,Google Scholar
  315. 315.
    Lee N-C (2018) Electromigration—The hurdle for miniaturization and high power devices. short course, IEMT, Melaka, Malaysia, 4–6 September 2018Google Scholar

Copyright information

© The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  • John H. Lau
    • 1
  • Ning-Cheng Lee
    • 2
  1. 1.Unimicron Technology CorporationTaoyuanTaiwan
  2. 2.Indium Corporation (United States)ClintonUSA

Personalised recommendations