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Field Programmable Gate Array (FPGA)-Based Fast and Low-Pass Finite Impulse Response (FIR) Filter

  • R. Raja SudharsanEmail author
  • J. Deny
Conference paper
  • 34 Downloads
Part of the Lecture Notes in Networks and Systems book series (LNNS, volume 118)

Abstract

The finite impulse response (FIR) filters are one among the digital filters which are widely proposed in field programmable gate array implementations. This paper presents the design of 4-tap and 8-bit fast low-pass FIR filter design under FPGA background using hardware description language (HDL). This design leads many applications like biomedical signals, pattern recognition, image processing and communications fields. The main attention of this FIR filter is focused towards the noise and performance constraints. In light of FPGA to accomplish FIR filter, not just considered the fixed capacity DSP-explicit chip constant, yet in addition the DSP processor adaptability. The blend FPGA and DSP innovation can further improve integration, increment work speed and framework abilities.

Keywords

Field programmable gate array (FPGA) Finite impulse response (FIR) Hardware description language (HDL) 

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Copyright information

© Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  1. 1.Department of Electronics and Communication Engineering, School of Electronics and Electrical TechnologyKalasalingam Academy of Research and EducationVirudhunagar (Dt)India

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