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Design of Super-Pipeline Architecture to Visualize the Effect of Dependency

  • Renuka PatelEmail author
  • Sanjay Kumar
Conference paper
  • 89 Downloads
Part of the Lecture Notes in Networks and Systems book series (LNNS, volume 107)

Abstract

Nowadays, pipelining is a very common phenomenon for getting speedup in processors. Super-pipeline architecture can issue more than one instruction in less than one clock cycle but dependency is major obstacle in super-pipeline architecture because dependency puts a stop in issuing the instruction in less than one clock cycle. In this paper, a simulator is designed for visualizing the effect of dependency on super-pipeline architecture. With the help of a simulator, we can make any previous instructions and instruction can be dependent on current instruction (dependency can be of any type like it can be of data dependency or control dependency or resource conflicts). Simulator also visualizes the effect of dependency for each instruction like how many numbers of stalls are encountered to handle dependency, in which cycle stall is encountered, how many clock cycles required to execute the instruction, and then finally, simulator calculates the performance parameters like total clock cycles, stalls, CPI, IPC, and speedup.

Keywords

Pipelining Super-pipeline Dependency CPI IPC 

References

  1. 1.
    N.P. Jouppi, D.W. Wall, Available instruction level parallelism for superscalar and superpipelined machines, in ASPLOS-III Proceedings of Third International Conference on Architectural Support for Programming Languages and Operating Systems (IEEE ACM, Boston, MA, USA, 1989), pp. 271–282Google Scholar
  2. 2.
    C.V. Ramamoorthy, H.F. Li, Pipeline architecture. ACM Comput. Surv. (CSUR) 9(1), 61–102 (1977)CrossRefGoogle Scholar
  3. 3.
    A. Briggs, K. Hwang, Computer Architecture and Parallel Processing (McGraw Hill, 2001), p. 148Google Scholar
  4. 4.
    M.J. Forsell, Minimal pipeline architecture—an alternative to Superscalar architecture. Microprocess. Microsyst. 20, 277–284 (1996) (Elsevier)CrossRefGoogle Scholar
  5. 5.
    J. Schneider, C. Ferdinand, Pipeline behavior prediction for superscalar processors by abstract interpretation, in Proceedings of the ACM SIGPLAN 1999 Workshop on Languages, Compilers, and Tools for Embedded Systems, vol. 34(7) (ACM, New York, NY, USA, 1999), pp. 35–44Google Scholar
  6. 6.
    A. Abnous, N. Bagherzadeh, Pipelining and bypassing in a VLIW processor. IEEE Trans. Parallel Distrib. Syst. 5(6), 658–664 (1994)CrossRefGoogle Scholar
  7. 7.
    V. Saravanan, D.P. Kothari, I. Woungang, An optimizing pipeline stall reduction algorithm for power and performance on multi-core CPUs. Hum. Cent. Comput. Inf. Sci. Springer Open J., 1–13 (2015)Google Scholar
  8. 8.
    R. Patel, S. Kumar, Visualizing effect of dependency in superscalar pipelining, in Proceedings of the 4th IEEE International Conference on Recent Advances in Information Technology RAIT (Indian Institute of Technology (ISM), Dhanbad, 2018), pp. 716–720. ISBN-978-1-5386-3038-9/18Google Scholar
  9. 9.
    L. Yizhen, L. Lin, W. Jun, The application of pipeline technology: an overview, in 2011 6th International Conference on Computer Science and Education (ICCSE) (IEEE Xplore, Singapore, 2011), pp. 47–51Google Scholar
  10. 10.
    K. Hwang, Advanced Computer Architecture (Tata McGraw Hill, 2001), pp. 288–289Google Scholar
  11. 11.
    R. Patel, S. Kumar, Simulation and investigation on effect of dependency in under pipelining. Int. J. Comput. Appl. (IJCA) 152(6), 12–15 (2016) (ISSN 0975-8887)Google Scholar
  12. 12.
    I.H. Unwala, E.E. Swartzlander, Superpipelined adder designs, in IEEE International Symposium on Circuits and Systems (ISCAS’93), 3–6 May 1993, pp. 1841–1844Google Scholar
  13. 13.
    V. Lee, N. Lam, F. Xiao, A.K. Somani, Superscalar and superpipelined microprocessor design, and simulation: a senior project. IEEE Trans. Educ. 40(1), 89–97 (1997)CrossRefGoogle Scholar
  14. 14.
    R. Patel, S. Kumar, The effect of dependency on scalar pipeline architecture. IUP J. Comput. Sci. 11(1), 38–50 (2017)Google Scholar
  15. 15.
    J.E. Thornton, The CDC 7600 project. IEEE Ann. Hist. Comput. 2(4), 338–348 (1980)CrossRefGoogle Scholar
  16. 16.
    S. Kumar, Mathematical modelling and simulation of a buffered fault tolerance double tree network, in 15th International Conference on Advanced Computing and Communications (IEEE, 2007), pp. 422–426Google Scholar
  17. 17.
    P.P. Change, D.M. Lavery, S.A. Mahlke, W.Y. Chen, W.M.W. Hwu, The importance of prepass code scheduling for superscalar and superpipelined processors. IEEE Trans. Comput. 44(3), 353–370 (1995)CrossRefGoogle Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  1. 1.Department of Computer SciencePt. Ravishankar Shukla UniversityRaipurIndia

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