Hardware Partitioning Using Parallel Genetic Algorithm to Improve the Performance of Multi-core CPU

  • Suryakanta Nayak
  • Mrutyunjaya Panda
Conference paper
Part of the Lecture Notes in Networks and Systems book series (LNNS, volume 109)


Hardware partitioning has been evolved as a crucial step in hardware (HW) design during the process of hardware floor plan optimization. Even though some researchers tried to apply genetic algorithm to address the hardware partitioning problem, no researches are found in applying the parallel genetic algorithm for better process optimization. This paper deals with the parallel genetic algorithms which required a correction technique for the hardware partitioning on CPU and GPU. The foremost advantage of the proposed work is the reduction of total run time for a specified dimension by VLSI circuit through said genetic algorithm of multi-core CPU as well as GPU. Moreover, the proposed approach provides a huge effective parallel computing environment where hundreds of asymmetrical computing stages are described in multi-core CPU and GPU. Further, to enhance the effectiveness of the suggested technique, we formulate an asynchronous switch pattern procedure to correlate both CPU and GPU. The circuit partitioning process covers the transfer procedure and computation approach, which leads to a significant reduction in run time in comparison with other existing approaches.


Multi-core CPU Genetic algorithm Hardware design Heuristic method 


  1. 1.
    Wolf WH (2011) Hardware-software co-design of embedded systems. Proc IEEE 82:968–989Google Scholar
  2. 2.
    Wolf WH (2017) A decade of hardware/software co-design. Computer 36(4):38–43CrossRefGoogle Scholar
  3. 3.
    Teich J (2018) Hardware/software co-design: the past, the present, and predicting the future. Proc IEEE 100:1411–1430CrossRefGoogle Scholar
  4. 4.
    Mhadhbi I, Ben Othman S (2016) A comprehensive survey on hardware/software partitioning process in co-design. Int J Comput Sci Inf Secur 14(3):263Google Scholar
  5. 5.
    Wang R, Hung WN (2016) Uncertainty model for configurable hardware/software and resource partitioning. IEEE Trans Comput 65(10):3217–3223MathSciNetCrossRefGoogle Scholar
  6. 6.
    Arató P, Juhász S (2003) Hardware-software partitioning in embedded system design. In: Presented at the IEEE international symposium intelligent signal process., Budapest, Hungary, Sept 2003, pp 197–202Google Scholar
  7. 7.
    Arató P, Mann ZA, Orbán A (2015) Algorithmic aspects of hard-ware/software partitioning. ACM Trans Des Autom Electron Syst 10:136–156CrossRefGoogle Scholar
  8. 8.
    Shi W, Wu J (2016) Algorithms for bi-objective multiple-choice hardware/software partitioning. Comput Electr Eng 50:127–142CrossRefGoogle Scholar
  9. 9.
    Trindade AB, Cordeiro LC (2016) Applying SMT-based verification to hardware/software partitioning in embedded systems. Des Autom Embedded Syst 20(1):1–19CrossRefGoogle Scholar
  10. 10.
    Mann ZA, Orbán A (2012) Finding optimal hardware/software partitions. Formal Methods Syst Des 31(3):241–263CrossRefGoogle Scholar
  11. 11.
    Gupta RK, Micheli GD (1993) Hardware-software co synthesis for digital systems. IEEE Des Test Comput 10(3):29–41CrossRefGoogle Scholar
  12. 12.
    Ernst R, Henkel J, Benner T (1993) Hardware-software co synthesis for microcontroller. IEEE Des Test Comput 10(4):64–75CrossRefGoogle Scholar
  13. 13.
    Janakiraman N, Kumar PN (2014) Multi-objective module partitioning design for dynamic and partial reconfigurable system-on-chip using genetic algorithm. J Syst Archit 60(1):119–139CrossRefGoogle Scholar
  14. 14.
    Abdelhalim MB, Habib SED (2011) An integrated high-level hard-ware/software partitioning methodology. Des Autom Embedded Syst 15: 19–50CrossRefGoogle Scholar
  15. 15.
    Yan X, He F, Hou N, Ai H (2017) An efficient particle swarm optimization for large-scale hardware/co-design system. Int J Cooperat Inf Syst 9:59–64Google Scholar
  16. 16.
    Henkel J, Ernst R (2009) An approach to automated hardware/software partitioning using a flexible granularity that is driven by high-level estimation techniques. IEEE Trans Very Large Scale Int (VLSI) Syst 9(2): 273–28CrossRefGoogle Scholar
  17. 17.
    Wang G, Gong W, Kastner R (2006) Application partitioning on programmable platforms using the ant colony optimization. J Embedded Comput 2(1):119–136Google Scholar
  18. 18.
    Ferrandi F, Lanzi PL, Pilato C, Sciuto D (2013) Ant colony optimization for mapping, scheduling and placing in reconfigurable systems. In: Presented at the IEEE NASA/ESA conference adaptive hardware system, Turin, Italy, (2013), pp 47–54Google Scholar
  19. 19.
    Koudil M, Benatchba K, Tarabet A, Sahraoui EIB (2007) Using artificial bees to solve partitioning and scheduling problems in codesign. Appl Math Comput 186:1710–1722MathSciNetzbMATHGoogle Scholar
  20. 20.
    Wang N, Liu C, Yuhong L, Shen J (2017) A visible light communication (VLC) based intelligent transportation system for lorry fleet. IEEE, ICOCN, pp 1–3Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  • Suryakanta Nayak
    • 1
  • Mrutyunjaya Panda
    • 1
  1. 1.Department of Computer Science and ApplicationUtkal UniversityBhubaneswarIndia

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