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Evolving Reversible Fault-Tolerant Adder Architectures and Their Power Estimation

  • S. Bharani Surya
  • C. Gokul Prasad
  • S. Raghul
  • N. MohankumarEmail author
Chapter
  • 31 Downloads
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 637)

Abstract

Fault tolerance property is incorporated in a circuit to increase its reliability. Error at the output side can be prevented by Fault-tolerant circuits. Its design enables the circuit to continue operation, at an error-free state, rather than failing completely, when some part of the circuit fails. Here, reversible adder fault-tolerant architectures of ripple carry, carry look-ahead adder (CLA) and carry skip adder (CSA) are implemented and their corresponding powers are estimated. Power efficiency and reliability of the implemented adders make them effective.

Keywords

Reversible computation Fault-tolerant circuit Low power 

References

  1. 1.
    Landauer, R.: Irreversibility and heat generation in the computing process. IBM J. Res. Dev. 5(3), 183–191 (1961)MathSciNetCrossRefGoogle Scholar
  2. 2.
    Mitra, S.K., Chowdhury, A.R.: Minimum cost fault tolerant adder circuits in reversible logic synthesis. In: 2012 25th International Conference on VLSI Design, Hyderabad, pp. 334–339 (2012)Google Scholar
  3. 3.
    Bennett, C.H.: Logical reversibility of computation. IBM J. Res. Dev. 17(6), 525–532 (1973)MathSciNetCrossRefGoogle Scholar
  4. 4.
    Shankar, A., Manchala, S., Mohan Kumar, N.: Low power implementation of DTMF chip by using power gating technique with merge flops. J. Eng. Appl. Sci. 13, 6335–6340 (2018)Google Scholar
  5. 5.
    Nayak, V.S.P., Ramchander, N., Reddy, R.S., Redy, T.H.S.P., Reddy, M.S.: Analysis and design of low-power reversible carry select adder using D-latch. In: 2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT), Bangalore, pp. 1917–1920 (2016)Google Scholar
  6. 6.
    Kaur, P., Dhaliwal, B.S.: Design of fault tolerant full adder/subtractor using reversible gates. In: 2012 International Conference on Computer Communication and Informatics, Coimbatore, pp. 1–5 (2012)Google Scholar
  7. 7.
    Chiwande, S.S., Dakhole, P.K.: VLSI design of power efficient carry skip adder using TSG & Fredkin reversible gate. In: 2012 International Conference on Devices, Circuits and Systems (ICDCS), Coimbatore, pp. 370–373 (2012)Google Scholar
  8. 8.
    Kunalan, D., Cheong, C.L., Chau, C.F., Ghazali, A.B.: Design of a 4-bit adder using reversible logic in quantum-dot cellular automata (QCA). In: 2014 IEEE International Conference on Semiconductor Electronics (ICSE2014), Kuala Lumpur, pp. 60–63 (2014)Google Scholar
  9. 9.
    Peres, A.: Reversible logic and quantum computers. Phys. Rev. A 32(6), 3266–3276 (1985)MathSciNetCrossRefGoogle Scholar
  10. 10.
    Paramasivan, D., Ravikumar, V., Ramesh, D., Ramya, H., Raghavan, R., Mohankumar, N.: Low power fault-tolerant reversible full adders. In: Proceedings of International Conference on Computing and Communication, Bangalore, June 2014Google Scholar
  11. 11.
    Thakral, S., Bansal, D.: Comparative study and implementation of BCD adders for reversible logic based ALU. In: 2017 2nd International Conference on Telecommunication and Networks (TEL-NET), Noida, pp. 1–5 (2017)Google Scholar
  12. 12.
    Somani, N., Chaudhary, C., Yadav, S.: Reversible adder design for ripple carry and carry look ahead (4, 8, 16, 32-bit). In: 2016 International Conference on Computing, Communication and Automation (ICCCA), Noida, pp. 1387–1392 (2016)Google Scholar
  13. 13.
    Vudadha, C., Phaneendra, P.S., Ahmed, S.E., Sreehari, V., Muthukrishnan, N.M., Srinivas, M.B.: Design and analysis of reversible ripple, prefix and prefix-ripple hybrid adders. In: 2012 IEEE Computer Society Annual Symposium on VLSI, Amherst, MA, pp. 225–230 (2012)Google Scholar
  14. 14.
    Manoj Kumar, S.B., et al.: Design and synthesis of reversible fault tolerant carry skip adder/subtractor. Int. J. Emerg. Sci. Eng. 1, 55–58 (2013)Google Scholar
  15. 15.
    Poornima, M., et al.: Fault-tolerant reversible logic for combinational circuits: a survey. In: Proceedings of International Conference on VLSI, Communication, Advanced Devices, Signals and Systems and Networking (2013)Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  • S. Bharani Surya
    • 1
  • C. Gokul Prasad
    • 2
  • S. Raghul
    • 1
  • N. Mohankumar
    • 1
    Email author
  1. 1.Department of Electronics and Communication Engineering, Amrita School of EngineeringAmrita Vishwa VidyapeethamCoimbatoreIndia
  2. 2.PPG Institute of TechnologyCoimbatoreIndia

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