Impact of Temperature on Circuit Metrics of Various Full Adders

  • M. Aalelai Vendhan
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 637)


This research work emphasizes the effect of temperature variation on circuit metrics of distinct 1-bit full adder circuits operating at low voltage. This work is studied using 90 nm MOSFET technology. The design styles employed for constructing the adders are conventional complementary metal-oxide semiconductor (CMOS), complementary pass-transistor logic (CPTL) and transmission gate (TG). Cadence Virtuoso is used for designing and simulation of the circuits. The circuit metrics such as average power, delay and power delay product (PDP) are calculated from the simulation results. On comparison of the results, it is evident that average power and PDP of CPTL adder remain least affected by temperature, while the delay of CMOS adder remains least affected by temperature.


Complementary pass transistor Propagation delay Average power Temperature variation 


  1. 1.
    Wu, S.H., Tetelbaum, A., Wang, L.C.: How does inverse temperature dependence affect timing sign-off. In: Amara, A., Ea, T., Belleville, M. (eds.) Emerging Technologies and Circuits. Lecture Notes in Electrical Engineering, vol. 66. Springer, Dordrecht (2010). Scholar
  2. 2.
    Kumar, R., Kursun, V.: Reversed temperature-dependent propagation delay characteristics in nanometer CMOS circuits. IEEE Trans. Circ. Syst. II Express Briefs 53(10), 1078–1082 (2006). Scholar
  3. 3.
    Park, C., John, J.P., Klein, K., Teplik, J., Caravella, J., Whitfield, J., Papworth, K., Cheng, S.: Reversal of temperature dependence of integrated circuits operating at very low voltages. In: Proceedings of International Electron Devices Meeting (1995).
  4. 4.
    Chinnery, D., Keutzer, K.: Overview of the factors affecting the power consumption. In: Closing the Power Gap Between ASIC & Custom. Springer, Boston, MA (2007). Scholar
  5. 5.
    Liao, W., He, L., Lepak, K.M.: Temperature and supply voltage aware performance and power modeling at microarchitecture level. IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 24(7), 1042–1053 (2005). Scholar
  6. 6.
    Morris Mano, M., Ciletti, M.D.: Digital Design: With an Introduction to the Verilog HDL, 5th edn, pp. 133–150. Pearson Education, New Jersey (2013)Google Scholar
  7. 7.
    Aalelai Vendhan, M.: Analysis on circuit metrics of 1-bit FinFET adders realized using distinct logic structures. Indian J. Sci. Technol. 12(26) (2019). Scholar
  8. 8.
    Hasan, M., Hossein, M.J., Saha, U.K., Tarif, M.S.: Overview and comparative performance analysis of various full adder cells in 90 nm technology. In: 2018 4th International Conference on Computing Communication and Automation (ICCCA) (2018).
  9. 9.
    Venkatesan, C., Thabsera, S.M., Sumithra, M.G., Suriya, M.: Analysis of 1-bit full adder using different techniques in Cadence 45 nm technology. In: 2019 5th International Conference on Advanced Computing & Communication Systems (ICACCS) (2019).

Copyright information

© Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringPanimalar Engineering CollegeChennaiIndia

Personalised recommendations