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Design of Generalized Rational Sampling Rate Converter Using Multiple Constant Multiplication

  • K. Gayathri
  • B. Aravind Krishna
  • Navin Kumar
Chapter
  • 37 Downloads
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 637)

Abstract

In this paper, a multirate sampling filter is designed by using multiple constant multiplication (MCM). This is achieved by replacing the multipliers in generalized rational sampling rate converter (GRSRC) with codes derived from MCM algorithm. Using the existing generalized rational sampling rate converter structure, we achieved reduced computational complexity since the delay requirements are significantly reduced. However, in order to lower the cost of the hardware, we used a multiplierless approach. In addition, the area utilization of this modified structure has been seen to be significantly reduced in comparison to that of the unintegrated structure with a comparable trade-off in terms of the speed and power requirement. Simulink model is developed, and FPGA implementation is completed. It is seen that the computational performance and many other parameters are improved.

Keywords

Multirate sampling Polyphase FIR filter Generalized sampling rate converter Multiple constant multiplication 

References

  1. 1.
    Bregovic, R., Yu, Y.J., Lim, Y.C., Saramaki, T.: Implementation of linear-phase FIR filters fro a rational sampling-rate conversion utilizing the coefficient symmetry. IEEE Trans. Circuits Syst. I Reg. Papers 58(3), 548–561 (2011)MathSciNetCrossRefGoogle Scholar
  2. 2.
    Bellanger, M.G., Bonnerot, G., Coudreuse, M.: Digital filtering by polyphse network: application to sample rate alteration and filter banks. IEEE Trans. Accoust. Speech Signal Process. ASSP-24(2), 109–114 (1976)CrossRefGoogle Scholar
  3. 3.
    Heightley, J.D.: Review of digital filtering. In: Annual Symposium on Frequency Control, April 1970Google Scholar
  4. 4.
    Schwinscackl, D., Kubin, G.: Polyphase representation of multirate nonlinear filters and its applications. IEEE Trans. Signal Process. 55, 2145–2157 (2007)MathSciNetCrossRefGoogle Scholar
  5. 5.
    Fiala, P.: High performance polyphase FIR filter structures in VHDL language for software defined radio based on FPGAGoogle Scholar
  6. 6.
    Gustafsson, O., Johansson, H.: Efficient implementation of FIR filter based rational sampling rate converters using constant matrix multiplication. In: Proceedings of 40th Fortieth Asilomar Conference on Signals, Systems and Computers, pp. 888–891, Oct 2006Google Scholar
  7. 7.
    Yim, W.H., Coakley, F.P., Evans, B.G.: Extended polyphase structures for multirate DSP. In: IEE Proceedings F (Radar and Signal Processing), vol. 139(4), pp. 273–277 (1992)Google Scholar
  8. 8.
    Jacob, P., Anoop, B.N.: Design and implementation of polyphase decimation filter. Int. J. Comput. Netw. Wirel. (April 2014)Google Scholar
  9. 9.
    Kaushal, P., Mehra, R.: Performance analysis of fractional sample rate converter using audio applications. IOSR J. Electr. Electron. Eng. (IOSR–JEEE) (Dec 2015)Google Scholar
  10. 10.
    Johannsson, H., Gockler, H.: Two stage based polyphase structures for arbitrary integer sampling rate conversion. IEEE Trans. Circuits Syst. (May 2015)Google Scholar
  11. 11.
    Bregovic, R., Saramaki, T., Yu, Y.J., Lim, Y.C.: An efficient implementation of linear-phase FIR filter for a rational sampling rate conversion. In: Proceedings of IEEE International Symposium on Circuits and Systems, pp. 5395–5398. Island of Kos, Greece (2006)Google Scholar
  12. 12.
    Kumar, A., Yadav, S., Purohit, N.: Generalised rational sampling rate conversion polyphase filters. IEEE Signal Process. Lett. 24(11) (2017)CrossRefGoogle Scholar
  13. 13.
    Voronenko, Y., Puschel, M.: Multiplier less multiple constant multiplication. ACM Trans. Algorithms 3(2) (2007)MathSciNetCrossRefGoogle Scholar
  14. 14.
    Marcos Peiro, M., Wanhammer, L.: High speed, low complexity FIR filter using multiplier block reduction and polyphase decomposition. In: IEEE International Symposium on Circuits and Systems, May 2000Google Scholar
  15. 15.
    Gustafsson, O., Dempster, A.G.: On the use of multiple constant multiplication in polyphase FIR filters and filter banks. In: Proceedings of 6th Nordic Signal Processing Symposium, 9–11 June, 2004Google Scholar
  16. 16.
    Dempster, A.G., Macleod, M.D.: Use of minimum-adder multiplier blocks in FIR digital filters. IEEE Trans. Circuits Syst. II, Analog. Digit. Signal Process. 42(9), 569–577 (1995)CrossRefGoogle Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  • K. Gayathri
    • 1
  • B. Aravind Krishna
    • 1
  • Navin Kumar
    • 1
  1. 1.Department of Electronics and Communication Engineering, Amrita School of EngineeringAmrita Vishwa VidyapeethamBengaluruIndia

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