Advertisement

The Implementation of a Configurable MBIST Controller for Multi-core SoC

  • Chunmei HuEmail author
  • Xiaoxuan Li
  • Zhigang Fu
  • Qianqian Tang
  • Rong Zhao
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 1146)

Abstract

Aiming at the problem of memory test power caused by the increasing proportion of embedded memory in multi-core SoC, this paper analyzes the existing issue and proposes a configurable MBIST controller to reduce test power consumption. This paper adopts MBIST configuration scan-chain to organize test groups and adopts a configurable PLL scan-chain to drive memories to its working frequency. Clock optimization method is also adopted to reduce test power. The method proposed has the advantages of low test power, flexible test configuration and less hardware added. The method can also diagnose the site of failing memories. The actual testing of the multi-core SoC on ATE V93000 shows that the proposed method effectively reduces power consumption, and meets the requirement of memory test.

Keywords

MBIST Group test Scan chain Test power consumption ATE test 

References

  1. 1.
    Li, J., Li, R., Yang, J., et al.: Low-power built-in self-test based on partial scan. Solid State Electron. Res. Prog. 25(1), 72–76 (2005)Google Scholar
  2. 2.
    Song, H., Shi, Y.: VLSI testability design technology for low-power BIST. Electron. Device 25(1), 101–104 (2002)Google Scholar
  3. 3.
    Qiu, H., Wang, C.: Pseudo-random test vector generation method based on built-in self-test. J. Huaiyin Teach. Coll.: Nat. Sci. Ed. 5(3), 212–215 (2006)Google Scholar
  4. 4.
    Zorian, Y.: A distributed BIST control scheme for complex VLSI devices. In: Proceedings of VLSI Test Symposium, pp. 4–9 (1993)Google Scholar
  5. 5.
    Girard, P.: Survey of low-power testing of VLSI circuits. Des. Test Comput. (IEEE) 19(3), 80–90 (2002)Google Scholar
  6. 6.
    Sun, H.: Research and Implementation of IP Core Low Power Test. National University of Defense Technology (2014)Google Scholar
  7. 7.
    Girard, P., Guiller, L., Landrault, G., et al.: Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity. In: IEEE International Symposium on Circuits and Systems, vol. 1, pp. 110–113 (1999)Google Scholar
  8. 8.
    Tan, E.M., Song, S.D., Shi, W.K.: A vector inserting TPG for BIST design with low peak power consumption. High-Tech Commun. (Engl.) 13(4), 418–421 (2007)Google Scholar
  9. 9.
    Hetherington, G., Fryars, T., Tamarapalli, N., et al.: Logic BIST for large industrial designs: real issues and case studies. In: Proceedings of International Test Conference, pp. 358–367 (1999)Google Scholar
  10. 10.
    Girard, P.: Survey of low-power testing of VLSI circuits. IEEE Des. Test Comput. 19(3), 82–92 (2002)CrossRefGoogle Scholar
  11. 11.
    Yuan, Q., Fang, L.: A method for effectively reducing the power consumption of memory BIST. Comput. Res. Dev. 49, 94–98 (2012)Google Scholar
  12. 12.
    Chen, F.: ATE-based FPGA test. Fudan University (2011)Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  • Chunmei Hu
    • 1
    Email author
  • Xiaoxuan Li
    • 2
  • Zhigang Fu
    • 1
  • Qianqian Tang
    • 1
  • Rong Zhao
    • 1
  1. 1.School of ComputerNational University of Defense TechnologyChangshaP.R. China
  2. 2.Xidian UniversityXianP.R. China

Personalised recommendations