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A Convolutional Neural Networks Accelerator Based on Parallel Memory

  • Hongbing Tan
  • Sheng LiuEmail author
  • Haiyan Chen
  • Honghui Sun
  • Hongliang Li
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 1146)

Abstract

Convolutional Neural Networks (CNNs) is one of the core algorithms for implementing artificial intelligence (AI), which has the characteristics of high parallelism and large amount of computations. With the rapid development of AI applications, general purpose processors such as CPU/GPU can’t meet the requirements for performance, power consumption and real-time performance of CNN. However, ASIC can fully exploit the parallelism of CNN and improve resource utilization to meet its requirements This paper has designed and implemented a new CNN accelerator based on parallel memory technology, which can support multiple parallelisms. A super processing unit (SPU) with kernel buffer and output buffer is proposed to make computation and data fetching more streamline then ensure the performance of accelerator. In addition, a two-dimensional buffer which can provide conflict-free non-aligned block access with different steps and aligned continuous access to meet the data requirements of varies parallelisms. The synthesis results show it can work at 1 GHz frequency with area overhead of 4.51 mm2 and on-chip buffer cost of 192 KB. We evaluated our design with varies CNN workloads, the efficiency of our design over 90% in most cases. Compared with the state-of-the-art accelerator architectures, the hardware cost of our design is smaller under the same performance.

Keywords

Convolution 2-D buffer Super processing unit Non-aligned block access Data-reusing 

Notes

Acknowledgment

This paper is supported by the National Science and Technology Major Project—intelligent computing unit for data center (cloud platform) and cluster computing (No. 2018ZX01031101) and the National Nature Science Foundation of China (No. 61602493, name: researches on efficient parallel memory techniques for wide vector dsps).

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Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  • Hongbing Tan
    • 1
  • Sheng Liu
    • 2
    Email author
  • Haiyan Chen
    • 2
  • Honghui Sun
    • 1
  • Hongliang Li
    • 1
  1. 1.Jiangnan Institute of Computing TechnologyWuxiChina
  2. 2.National University of Defense TechnologyChangshaChina

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