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Novel Reversible ALU Architecture Using DSG Gate

  • Shaveta ThakralEmail author
  • Dipali Bansal
Conference paper
  • 15 Downloads
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 1097)

Abstract

In the era of giant-scale integration and technology advancement, it will not be economically feasible to cope up as power dissipation is a fundamental threat to the technology. The impending end of Moore’s law is motivating to seek for better technology. Reversible logic provides dramatic improvements in energy efficiency and proves to be a promising solution for the future. The most promising application of reversible logic will be for smart and massive quantum computing applications in near future. Implementing reversible logic is an intractable research problem, but many researchers have chosen this path to save energy and decided to blaze into this new trail of technology. The arithmetic and logic unit (ALU) is command center of all computing environment. The most important aspects of ALU like number of operations, ancillary inputs, garbage outputs and quantum cost are mostly discussed to compare whether any reversible logic-based ALU is more efficient over other. This paper presents a novel reversible ALU where these aspects have been examined, and optimization metrics comparison shows the significant improvements over existing designs. The proposed ALU design is coded in Verilog HDL, synthesized and simulated using electronic design automation (EDA) tool—Xilinx ISE design suit 14.2. RCViewer + tool has been used to validate quantum cost of proposed design.

Keywords

Power dissipation ALU Reversible logic Optimization Ancillary 

References

  1. 1.
    Landauer, R. 1961. Irreversibility and heat generation in the computing process. IBM Journal of Research and Development 5: 183–191.MathSciNetCrossRefGoogle Scholar
  2. 2.
    Bennett, C. 1973. Logical reversibility of computation. IBM Journal of Research and Development 17: 525–532.MathSciNetCrossRefGoogle Scholar
  3. 3.
    Syamala, Y., and A. Tilak. 2011. Reversible arithmetic logic unit. In: 3rd international conference on electronics computer technology (ICECT), 207–211, IEEE.Google Scholar
  4. 4.
    Morrison, M., M. Lewandowski, R. Meana, and N. Ranganathan. 2011. Design of a novel reversible ALU using an enhanced carry lookahead adder. 2011 11th IEEE international conference on nanotechnology, 1436–1440. Portland, Oregon, USA: IEEE.CrossRefGoogle Scholar
  5. 5.
    Singh, R., S. Upadhyay, K. Jagannath, and S. Hariprasad. 2014. Efficient design of arithmetic logic unit using reversible logic gates. International Journal of Advanced Research in Computer Engineering & Technology (IJARCET) 3.Google Scholar
  6. 6.
    Moallem, P., M. Ehsanpour, A. Bolhasani, and M. Montazeri. 2014. Optimized reversible arithmetic logic units. Journal of Electronics (China) 31: 394–405.CrossRefGoogle Scholar
  7. 7.
    Sen, B., M. Dutta, M. Goswami, and B. Sikdar. 2014. Modular design of testable reversible ALU by QCA multiplexer with increase in programmability. Microelectronics Journal 45: 1522–1532.CrossRefGoogle Scholar
  8. 8.
    Guan, Z., W. Li, W. Ding, Y. Hang, and L. Ni. 2011. An arithmetic logic unit design based on reversible logic gates. In: IEEE Pacific rim conference on communications, computers and signal processing (PacRim), 925–931, IEEE.Google Scholar
  9. 9.
    Gupta, A., U. Malviya, and V. Kapse. 2012. Design of speed, energy and power efficient reversible logic based vedic ALU for digital processors. In (NUiCONE), 1–6, IEEE.Google Scholar
  10. 10.
    Gopal, L., N. Syahira, M. Mahayadin, A. Chowdhury, A. Gopalai, and A. Singh. 2014. Design and synthesis of reversible arithmetic and logic unit (ALU). In International conference on computer, communications, and control technology (I4CT), 289–293, IEEE.Google Scholar
  11. 11.
    Thakral, S., and D. Bansal. 2016. Fault tolerant ALU using parity preserving reversible logic gates. International Journal of Modern Education and Computer Science 8: 51–58.CrossRefGoogle Scholar
  12. 12.
    Sasamal, T., A. Singh, and A. Mohan. 2016. Efficient design of reversible ALU in quantum-dot cellular automata. Optik 127: 6172–6182.CrossRefGoogle Scholar
  13. 13.
    Shukla, A., and M. Saxena. 2016. Efficient reversible ALU based on logic gate structure. International Journal of Computer Applications 150 (2): 32–36.CrossRefGoogle Scholar
  14. 14.
    Thakral, S., D. Bansal, and S. Chakarvarti. 2016. Implementation and analysis of reversible logic based arithmetic logic unit. TELKOMNIKA (Telecommunication Computing Electronics and Control) 14: 1292–1298.CrossRefGoogle Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  1. 1.Department of Electronics & Communication (FET)Manav Rachna International Institute of Research & StudiesFaridabadIndia

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