Performance Analysis of Data Communication Using Hybrid NoC for Low Latency and High Throughput on FPGA

  • C. AmareshEmail author
  • Anand Jatti
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 1040)


The perception of the theory of communication network has led to enormous supplanting committed to simplex, duplex system in terms of various scales of interconnecting systems and switches. Each data interactive system needs to have a smart way for the design of efficient and tolerant system in terms of adaptability, versatility, execution, and effective data delivery. In this peculiarity, the system architects demand for a novel network on-chip router which is error free and minimized circuit path with greater packet delivery ratio, minimum delay, and better bandwidth utilization. In this paper, we propose the modeling of network architecture in consideration with 8 × 8 switch router which indulges the suitable algorithm for shortest path finder, i.e., minimum spanning tree, for efficient routing in run-time. We have demonstrated warmhole technique and virtual cut-through mechanisms for automatic correction with validating errors. So, we have selected verilog HDL for development under the environment of VIVADO Xilinx 2018-1 and demonstrated on Nexys DDR-4 Artix-7 Field Programmable Gate Array family bearing part number XCA7CGS100t comprised of 324 pins with the results it is noticed that better reliability and minimized latency of 36.5% with enhanced throughput reaching 40% than the existing router. The proposed design is acceptable in terms of better performance in terms of area, delay, and resource allocation.


Communication switch Error FPGA HDL NoC Router Shortest path algorithm Topology Switching Power reduction schemes and encoder and decoder 


  1. 1.
    Modarressi, M., A hybrid packet-circuit switched on-chip network based on SDM. 978-3-9810801-5-5/DATE09, 2009 EDAAGoogle Scholar
  2. 2.
    Kuma, S.: A network on chip architecture and design methodology. In: Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI’02). IEEE (2002). 0-7695-1486-3/02Google Scholar
  3. 3.
    Lotfi-Kamran, P.: An efficient hybrid-switched network-on-chip for chip multiprocessors. IEEE Trans. Comput. 65(5), 1656–1662 (2016)MathSciNetCrossRefGoogle Scholar
  4. 4.
    Shin, K.G., et al.: Investigation and implementation of hybrid switching. IEEE Trans. Comput. 45(6) (1996)CrossRefGoogle Scholar
  5. 5.
    Agyeman, M.O., et al.: Broadening the performance of hybrid NoCs past the limitations of network heterogeneity. J. Low Power Electron. Appl. 7, 8 (2017). Scholar
  6. 6.
    FallahRad, M., et al.: In: 2016 Euromicro Conference on Digital System Design. IEEE (2016). 978-1-5090-2817-7/16,
  7. 7.
    Aghdai, A., et al.: Structure of a Hybrid Modular Switch. arXiv:1705.09999v1 [cs.NI], 28 May 2017
  8. 8.
    Biswas, A.K.: Proficient timing channel protection for hybrid (packet/circuit-switched) network-on-chip. IEEE Trans. Parallel Distrib. Syst. (2017)Google Scholar
  9. 9.
    Ezhumalai, P., et al.: Superior hybrid two layer router architecture for FPGAs using network-on-chip. (IJCSIS) Int. J. Comput. Sci. Inf. Secur. 7(1) (2010)Google Scholar
  10. 10.
    Paramasivam, K.: System on-chip and its research challenges. ICTACT J. Microelectron. 01(02) (2015)Google Scholar
  11. 11.
    Tsai, W.-C., et al.: Systems on chips: structure and design methodologies. J. Electr. Comput. Eng. 2012, 15 (2012). Article ID 509465, (Hindawi Publishing Corporation)CrossRefGoogle Scholar
  12. 12.
    Mikkel, B., et al.: ReNoC: a network-on-chip architecture with reconfigurable topology. In: Second ACM/IEEE International Symposium on Networks-on-Chip. IEEE (2008). 978-0-7695-3098-7/08,
  13. 13.
    Lusala, A.K., et al.: Joining SDM-based circuit switching with packet switching in a router for on-chip networks. Int. J. Reconfigurable Comput. 2012, 16. Article ID 474765, (Hindawi Publishing Corporation)CrossRefGoogle Scholar
  14. 14.
    William, J., et al.: Course packets, not wires: on-chip interconnection networks. DAC 2001, 18–22 June 2001, Las Vegas, Nevada, USA. Copyright 2001 ACM 1-58113-297-2/01/0006Google Scholar

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© Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  1. 1.R.V. College of EngineeringBangaloreIndia

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