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ICDSMLA 2019 pp 1947-1958 | Cite as

Iterative Analysis of Optimization Algotithms for Placement and Routing in Asic Design

  • Shaik KarimullahEmail author
  • D. Vishnuvardhan
Conference paper
  • 2 Downloads
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 601)

Abstract

The idea of Optimizing the complexity and reduction in area of Integrated Circuits plays dominant role in the process of fabrication and it provides significant challenges for researchers and engineers to come-up with different types of optimization techniques in the area of Very Large Scale Integration System Design for the betterment of Area, Time and power. This paper provides Iterative analysis and performance comparison of Optimization algorithms named Descrete State Transition, Nearest Neighbour and Simulated Annealing. This search process has been carried out to estimate the time taken to enable a logic block at least once with different number of iterations for the three optimization algorithms using MATLSB software with TSP tool box.

Keywords

Logic block Iterative analysis Search process Simulated annealing DST Nearest neighbor TSP tool box 

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Copyright information

© Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  1. 1.JNTUA AnanthapuramuAnanthapuramuIndia
  2. 2.Department of ECEJNTUAAnanthapuramuIndia

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