Advertisement

Novel Application of FeFETs to NAND Flash Memory Circuits

  • Shigeki SakaiEmail author
  • Mitsue Takahashi
Chapter
  • 30 Downloads
Part of the Topics in Applied Physics book series (TAP, volume 131)

Abstract

A 64 kbit (kb) one-transistor-type ferroelectric memory array and peripheral logic circuits were integrated and characterized. N-channel Pt/SrBi2Ta2O9/Hf–Al–O/Si ferroelectric-gate field-effect transistors (FeFETs) were used as the memory cells. The array was designed as a NAND flash memory, which had 32 blocks and 8 word lines × 256 bit lines per block. The bit-line and block selector logic circuits were represented by logic NOT and NAND units that were constructed by the complimentary structure of an n-channel FeFET and a p-channel FeFET. The erase, program, and nondestructive read operations were demonstrated for all blocks. The reading of the memory cells showed a clear separation of their erased and all “1”-programmed states. Threshold-voltage retention of one block showed no significant degradation after 2 days. To program arbitrary “1” and “0” patterns a single-cell self-boost program scheme was introduced that can reduce program-disturb and power dissipation, and in fact very low program-inhibit-bit-line voltage (≤1.0 V) was achieved. Using this scheme the memory cells were programmed in “1” and “0” checkered pattern, and two distinguishable threshold-voltage distributions of 1 block (2 k cells) could be read out.

Notes

Acknowledgements

This work was partially supported by New Energy and Industrial Technology Development Organization.

References

  1. 1.
    Y. Tarui, T. Hirai, K. Teramoto, H. Koike, and K. Nagashima: Appl. Surf. Sci. 113, 656 (1997).Google Scholar
  2. 2.
    J.F. Scott, Ferroelectric Memories (Springer, Berlin, 2000) Chap. 12, p. 175Google Scholar
  3. 3.
    S. Sakai, R. Ilangovan, IEEE Electron Device Lett. 25 369 (2004)Google Scholar
  4. 4.
    M. Okuyama, Y. Ishibashi (eds.), Ferroelectric Thin Films—Basic Properties and Device Physics for Memory Applications (Springer, Berlin, 2005) Part 4, p. 219Google Scholar
  5. 5.
    S. Sakai, Adv. Sci. Technol. 45, 2382 (2006)Google Scholar
  6. 6.
    H. Ishiwara, Curr. Appl. Phys. 9, S2 (2009)Google Scholar
  7. 7.
    S. Sakai, M. Takahashi, Materials 3, 4950 (2010)Google Scholar
  8. 8.
    T. Hatanaka, R. Yajima, T. Horiuchi, S. Wang, X. Zhang, M. Takahashi, S. Sakai, K. Takeuchi, IEEE J. Solid-State Circuits, 45, 2156 (2010)Google Scholar
  9. 9.
    T.S. Böscke, J. Müller, D. Bräuhaus, U. Schröder, U. Böttger, IEDM Tech. Dig. (2011), p. 547Google Scholar
  10. 10.
    S. Sakai, X. Zhang, L.V. Hai, W. Zhang, M. Takahashi, in Proceedings of the 12th IEEE Annual Non-volatile Memory Technology Symposium (2012), p. 55.Google Scholar
  11. 11.
    S. Sakai, US Patent 7,226,795 (2005)Google Scholar
  12. 12.
    S. Sakai, R. Ilangovan, M. Takahashi, Jpn. J. Appl. Phys. 43, 7876 (2004)Google Scholar
  13. 13.
    S. Sakai, M. Takahashi, R. Ilangovan, IEDM Tech. Dig., 915 (2004)Google Scholar
  14. 14.
    M. Takahashi, S. Sakai, Jpn. J. Appl. Phys. 44, L800 (2005)Google Scholar
  15. 15.
    Q.-H. Li, S. Sakai, Appl. Phys. Lett. 89, 222910 (2006)Google Scholar
  16. 16.
    T. Horiuchi, M. Takahashi, Q.-H. Li, S. Wang, S. Sakai, Semicond. Sci. Technol. 25, 055005 (2010)Google Scholar
  17. 17.
    Q.-H. Li, M. Takahashi, T. Horiuchi, S. Wang, S. Sakai, Semicond. Sci. Technol. 23, 045011 (2008)Google Scholar
  18. 18.
    Q.-H. Li, T. Horiuchi, S. Wang, M. Takahashi, S. Sakai, Semicond. Sci. Technol. 24, 025012 (2009)Google Scholar
  19. 19.
    M. Takahashi, T. Horiuchi, Q.-H. Li, S. Wang, K.-Y. Yun, S. Sakai, Electron. Lett. 44, 467 (2008)Google Scholar
  20. 20.
    M. Takahashi, S. Wang, T. Horiuchi, S. Sakai, IEICE Electron. Express 6, 831 (2009)Google Scholar
  21. 21.
    L.V. Hai, M. Takahashi, S. Sakai, Semicond. Sci. Technol. 25, 115013 (2010)Google Scholar
  22. 22.
    L.V. Hai, M. Takahashi, S. Sakai, in Proceedings of 3rd IEEE International Memory Workshop, 2011, p. 175.Google Scholar
  23. 23.
    L.V. Hai, M. Takahashi, W. Zhang, S. Sakai, Semicond. Sci. Technol. 30, 015024 (2015)Google Scholar
  24. 24.
    L.V. Hai, M. Takahashi, W. Zhang, S. Sakai, Jpn. J. Appl. Phys. 54, 088004 (2015)Google Scholar
  25. 25.
    S. Sakai, M. Takahashi, K. Takeuchi, Q.H. Li, T. Horiuchi, S. Wang, K.Y. Yun, M. Takamiya, T. Sakurai, in Proceedings of 23rd IEEE Non-volatile Semiconductor Memory Workshop: 3rd International Conference on Memory Technology and Design (2008), p. 103.Google Scholar
  26. 26.
    S. Wang, M. Takahashi, Q.-H. Li, K. Takeuchi, S. Sakai, Semicond. Sci. Technol. 24 105029 (2009)Google Scholar
  27. 27.
    K. Miyaji, S. Noda, T. Hatanaka, M. Takahashi, S. Sakai, K. Takeuchi, Solid-State Electron. 58, 34 (2011)Google Scholar
  28. 28.
    X.-Z. Zhang, K. Miyaji, M. Takahashi, K. Takeuchi, S. Sakai, in Proceedings of 3rd IEEE International Memory Workshop (2011), p. 155.Google Scholar
  29. 29.
    X. Zhang, M. Takahashi, S. Sakai, Integrated Ferroelectr. 132, 114 (2012)Google Scholar
  30. 30.
    X. Zhang, M. Takahashi, K. Takeuchi, S. Sakai, Jpn. J. Appl. Phys. 51, 04DD01 (2012)Google Scholar
  31. 31.
    K. Imamiya, H. Nakamura, T. Himeno, T. Yamamura, T. Ikehashi, K. Takeuchi, K. Kanda, K. Hosono, T. Futatsuyama, K. Kawai, R. Shirota, N. Arai, F. Arai, K. Hatakeyama, H. Hazama, M. Saito, H. Meguro, K. Conley, K. Quader, J.J. Chen, IEEE J. Solid-State Circuits 37, 1493 (2002)Google Scholar
  32. 32.
    International Technology Roadmap for Semiconductors 2007 Edition, Process Integration, Devices, and Structures. Table PIDS5a Non-volatile Memory Technology Requirements Near-term YearsGoogle Scholar
  33. 33.
    S. Wang, M. Takahashi, S. Sakai, unpublishedGoogle Scholar
  34. 34.
    X. Zhang, M. Takahashi, S. Sakai, unpublishedGoogle Scholar
  35. 35.
    T. Tanaka, Y. Tanaka, H. Nakamura, K. Sakui, H. Oodaira, R. Shirota, K. Ohuchi, F. Masuoka, H. Hara, IEEE J. Solid-State Circuits 29, 1366 (1994)Google Scholar
  36. 36.
    M. Momodomi, T. Tanaka, Y. Iwata, Y. Tanaka, H. Oodaira, Y. Itoh, R. Shirota, K. Ohuchi, F. Masuoka, IEEE J. Solid-State Circuits 26 492 (1991)Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  1. 1.National Institute of Advanced Industrial Science and TechnologyTsukubaJapan

Personalised recommendations